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參數(shù)資料
| 型號(hào)： | IDT72V06L25JI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ASYNCH 8192X18 25NS 32PLCC |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲(chǔ)容量： | 144K（16K x 9） |
| 訪問時(shí)間： | 25ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 32-PLCC（13.97x11.43） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V06L25JI8 |
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
OPERATING MODES:
Caremustbetakentoassurethattheappropriateflagismonitoredbyeach
system (i.e. FFis monitored on the device where Wis used; EFis monitored
onthedevicewhereRisused).Foradditionalinformation,refertoTechNote
8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note
6: Designing with FIFOs.
SINGLE DEVICE MODE
A single IDT72V01/72V02/72V03/72V04/72V05/72V06 may be used
when the application requirements are for 512/1,024/2,048/4,096/8,192/
16,384wordsorless.ThesedevicesareinaSingleDeviceConfigurationwhen
the Expansion In ( XI) control input is grounded (see Figure 12).
TheseFIFOscaneasilybeadaptedtoapplicationswhentherequirements
are for greater than 512/1,024/2,048/4,096/8,192/16,384 words. Figure 14
demonstratesDepthExpansionusingthreeIDT72V01/72V02/72V03/72V04/
72V05/72V06s. Any depth can be attained by adding additional IDT72V01/
72V02/72V03/72V04/72V05/72V06s. These devices operate in the Depth
Expansionmodewhenthefollowingconditionsaremet:
1. ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(FL)control
input.
2. All other devices must have FLin the HIGH state.
3. TheExpansionOut(XO)pinofeachdevicemustbetiedtotheExpansion
In ( XI ) pin of the next device. See Figure 14.
4. ExternallogicisneededtogenerateacompositeFullFlag(FF)andEmpty
Flag ( EF). This requires the ORing of all EFs and ORing of all FFs (i.e.
allmustbesettogeneratethecorrectcompositeFForEF). SeeFigure14.
5. The Retransmit ( RT) function and Half-Full Flag ( HF) are not available
in the Depth Expansion Mode.
Foradditionalinformation,refertoTechNote9: CascadingFIFOsorFIFO
Modules.
USAGE MODES:
WIDTH EXPANSION
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlsignalsofmultipledevices. Statusflags(EF,FFandHF)canbedetected
from any one device. Figure 13 demonstrates an 18-bit word width by using
twoIDT72V01/72V02/72V03/72V04/72V05/72V06s. Anywordwidthcanbe
attainedbyaddingadditionalIDT72V01/72V02/72V03/72V04/72V05/72V06s
(Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT72V01/72V02/72V03/72V04/72V05/72V06sasshowninFigure16.Both
Depth Expansion and Width Expansion may be used in this mode.
DATAFLOW-THROUGH
Twotypesofflow-throughmodesarepermitted,areadflow-throughand
writeflow-throughmode. Forthereadflow-throughmode(Figure17),theFIFO
permitsareadingofasinglewordafterwritingonewordofdataintoanempty
FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of
W,calledthefirstwriteedge,anditremainsonthebusuntilthe Rlineisraised
fromLOW-to-HIGH,afterwhichthebuswouldgointoathree-statemodeafter
tRHZ ns. The EFline would have a pulse showing temporary deassertion and
then would be asserted.
Inthewriteflow-throughmode(Figure18),theFIFOpermitsthewritingof
asinglewordofdataimmediatelyafterreadingonewordofdatafromafullFIFO.
The Rline causes the FFto be deasserted but the Wline being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge
ofW,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhenFF
isnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer.
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| IDT72V06L35J | 功能描述:IC ASYNCH 8192X18 35NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V06L35J8 | 功能描述:IC ASYNCH 8192X18 35NS 32PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V201L10J | 功能描述:IC FIFO SYNC 256X9 10NS 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:80 系列:7200 功能:同步 存儲(chǔ)容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
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