IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 1" />
參數(shù)資料
型號(hào): IDT72V205L10PFG8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 11/25頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 16KX9 10NS 64QFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步
存儲(chǔ)容量: 144K(16K x 9)
訪問(wèn)時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 72V205L10PFG8
19
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK
and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENH
tCLKH
tCLKL
WEN
PAF
RCLK
REN
4294 drw 23
tENS
tENH
tENS
D - (m + 1) Words in FIFO
D - m Words in FIFO
tPAFS
D - (m + 1) Words
in FIFO
tPAFS
tSKEW2
(3)
tPAFS
WCLK
tENH
tCLKH
tCLKL
WEN
PAE
RCLK
REN
4294 drw 22
tENS
tENH
tENS
n words in FIFO(2),
n + 1words in FIFO(3)
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
tSKEW2
tPAES
n Words in FIFO(2),
n + 1 words in FIFO(3)
(4)
tPAES
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