參數(shù)資料
型號(hào): IDT72V205L20TF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/25頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 16KX9 20NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 72V
功能: 異步
存儲(chǔ)容量: 144K(16K x 9)
訪問(wèn)時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V205L20TF8
1
MARCH 2013
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4294/7
3.3 VOLT CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
FEATURES:
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OFFSET REGISTER
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
WEN
WCLK
D0-D17
LD
RS
(
HF)/WXO
WXI
REN
RCLK
OE
Q0-Q17
RXO
RXI
FL
4294 drw 01
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-
patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local
AreaNetworks(LANs),andinterprocessorcommunication.
TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).
TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.
AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol
oftheoutput.
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