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參數(shù)資料
| 型號： | IDT72V215L15TFI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 25/25頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO SYNC 512X18 15NS 64STQFP |
| 標準包裝： | 1,250 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 9.2K（512 x 18） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V215L15TFI8 |
9
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Figure 2. Writing to Offset Registers
LD
WEN
WCLK
Selection
0
Writingtooffsetregisters:
EmptyOffset
FullOffset
0
1
NoOperation
1
0
Write Into FIFO
1
NoOperation
Figure 3. Offset Register Location and Default Values
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place.TheHalf-FullFlag(HF)andProgrammableAlmost-FullFlag(PAF)will
beresettoHIGHaftertRSF.TheProgrammableAlmost-EmptyFlag(PAE)will
be reset to LOW after tRSF. The Full Flag (FF) will reset to HIGH. The Empty
Flag(EF)willresettoLOWinIDTStandardmodebutwillresettoHIGHinFWFT
mode. Duringreset,theoutputregisterisinitializedtoallzerosandtheoffset
registersareinitializedtotheirdefaultvalues.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transitionofWCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. TheFF flag is updated on the rising
edgeofWCLK.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOWallowingawritetooccur. TheIRflagisupdatedontherisingedgeofWCLK.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
READ CLOCK (RCLK)
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdataand
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
furtherreadoperations. RENisignoredwhentheFIFOisempty. Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated
on the rising edge of RCLK.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH
transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrue read(RCLKwith REN=LOW),inhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister.WhenOEisdisabled(HIGH),theQoutput
databusisinahigh-impedancestate.
LOAD (LD)
The IDT72V205/72V215/72V225/72V235/72V245 devices contain two
12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs. Whenthe
Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is
writtenintotheEmptyOffsetregisteronthefirstLOW-to-HIGHtransitionofthe
Write Clock (WCLK). When the LD pin and WEN are held LOW then data is
written into the Full Offset register on the second LOW-to-HIGH transition of
WCLK.ThethirdtransitionofWCLKagainwritestotheEmptyOffsetregister.
However,writingalloffsetregistersdoesnothavetooccuratonetime.One
ortwooffsetregisterscanbewrittenandthenbybringingtheLDpinHIGH,the
FIFOisreturnedtonormalread/writeoperation.WhentheLDpinissetLOW,
and WEN is LOW, the next offset register in sequence is written.
EMPTY OFFSET REGISTER
17
11
0
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
FULL OFFSET REGISTER
17
11
0
DEFAULT VALUE
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
4294 drw 04
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
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