參數(shù)資料
型號: IDT72V221L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/14頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 1KX9 15NS 32QFP
標準包裝: 2,000
系列: 72V
功能: 同步
存儲容量: 9K(1K x 9)
訪問時間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 72V221L15PF8
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
8
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
tRS
tRSR
RS
REN1,
REN2
tRSF
OE = 1
OE = 0
(2)
EF, PAE
FF, PAF
Q0 - Q8
4092 drw06
WEN1
(1)
tRSS
tRSF
tRSR
tRSS
tRSR
tRSS
WEN2/
LD
tDH
tENH
tSKEW1(1)
tCLK
tCLKH
tCLKL
tDS
tENS
tWFF
WCLK
D0 - D8
WEN1
WEN2/
(If Applicable)
FF
RCLK
REN1,
REN2
NO OPERATION
4092 drw07
DATA IN VALID
tENH
tENS
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IDT72V221L15PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP
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