- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10171 > IDT72V221L15PFG (IDT, Integrated Device Technology Inc)IC FIFO SYNC 1KX9 15NS 32QFP PDF資料下載
參數(shù)資料
| 型號： | IDT72V221L15PFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 1KX9 15NS 32QFP |
| 標準包裝： | 1 |
| 系列： | 72V |
| 功能： | 同步 |
| 存儲容量： | 9K（1K x 9） |
| 訪問時間： | 15ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1255 (CN2011-ZH PDF) |
| 其它名稱： | 72V221L15PFG 800-1516 |
13
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
thisconfiguration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatReset
so that the pin operates as a control to load and read the programmable flag
offsets.
Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
OPERATINGCONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be
usedwhentheapplicationrequirementsarefor256/512/1,024/2,048/4,096/
8,192wordsorless. WhentheseFIFOsareinaSingleDeviceConfiguration,
1,024/2,048/4,096/8,192words. Theexistenceoftwoenablepinsontheread
andwriteportallowdepthexpansion. TheWriteEnable2/Loadpinisusedas
a second write enable in a depth expansion configuration thus the program-
mableflagsaresettothedefaultvalues. Depthexpansionispossiblebyusing
oneenableinputforsystemcontrolwhiletheotherenableinputiscontrolledby
expansionlogictodirecttheflowofdata. Atypicalapplicationwouldhavethe
expansionlogicalternatedataaccessfromonedevicetothenextinasequential
manner. TheseFIFOsoperateintheDepthExpansionconfigurationwhenthe
followingconditionsaremet:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
operatesasecondWriteEnable.
2. External logic is used to control the flow of data.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-
CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails
ofthisconfiguration.
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput
controlssignalsofmultipledevices. Acompositeflagshouldbecreatedforeach
oftheend-pointstatusflags(EFandFF). Thepartialstatusflags(AEandAF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
widthbyusingtwoIDT72V201/72V211/72V221/72V231/72V241/72V251s.
Any word width can be attained by adding additional IDT72V201/72V211/
72V221/72V231/72V241/72V251s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
configuration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatResetso
thatthepinoperatesasacontroltoloadandreadtheprogrammableflagoffsets.
DEPTH EXPANSION
The IDT72V201/72V211/72V221/72V231/72V241/72V251 can be
adaptedtoapplicationswhentherequirementsareforgreaterthan256/512/
Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO
DATA OUT (Q0 - Q8)
DATA IN (D0 - D8)
RESET (
RS)
READ CLOCK (RCLK)
READ ENABLE 1 (
REN1)
OUTPUT ENABLE (
OE)
EMPTY FLAG (
EF)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
READ ENABLE 2 (
REN2)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (
WEN1)
WRITE ENABLE 2/LOAD (WEN2/
LD)
FULL FLAG (
FF)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72V201
72V211
72V221
72V231
72V241
72V251
4092 drw16
DATA IN (D)
WRITE CLOCK (WCLK)
18
9
RESET (
RS)
READ CLOCK (RCLK)
DATA OUT (Q)
9
18
READ ENABLE 2 (
REN2)
READ ENABLE 2 (
REN2)
WRITE ENABLE1 (
WEN1)
FULL FLAG (
FF) #1
PROGRAMMABLE (
PAF)
PROGRAMMABLE (
PAE)
EMPTY FLAG (
EF) #2
OUTPUT ENABLE (
OE)
READ ENABLE1 (
REN1)
9
WRITE ENABLE2/LOAD (WEN2/
LD)
FULL FLAG (
FF) #2
EMPTY FLAG (
EF) #1
RESET (
RS)
4092 drw17
IDT
72V201
72V211
72V221
72V231
72V241
72V251
IDT
72V201
72V211
72V221
72V231
72V241
72V251
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1276ACSW#TRPBF | IC A/D CONV 12BIT SAMPLNG 24SOIC |
| LTC1276ACSW#TR | IC ADC 12BIT SAMPLING REF 24SOIC |
| VI-260-CU-F4 | CONVERTER MOD DC/DC 5V 200W |
| VI-27Y-MX | CONVERTER MOD DC/DC 3.3V 49.5W |
| SP3224EEA-L | IC TXRX RS232 ESD 20SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V221L15PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP |
| IDT72V221L15PFI | 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
| IDT72V221L15PFI8 | 功能描述:IC FIFO SYNC 1KX9 15NS 32QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:80 系列:7200 功能:同步 存儲容量:18.4K（1K x 18） 數(shù)據(jù)速率:- 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（10x10） 包裝:托盤 其它名稱:72225LB10TF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。