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    參數(shù)資料
    型號: IDT72V225L15PFI
    廠商: IDT, Integrated Device Technology Inc
    文件頁數(shù): 17/25頁
    文件大小: 0K
    描述: IC FIFO SYNC 1024X18 15NS 64TQFP
    標準包裝: 90
    系列: 72V
    功能: 同步
    存儲容量: 18.4K(1K x 18)
    訪問時間: 15ns
    電源電壓: 3 V ~ 3.6 V
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 64-LQFP
    供應商設備封裝: 64-TQFP(14x14)
    包裝: 托盤
    其它名稱: 72V225L15PFI
    24
    IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
    256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
    COMMERCIALANDINDUSTRIAL
    TEMPERATURERANGES
    MARCH 2013
    Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
    Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration
    Dn
    INPUT READY
    WRITE ENABLE
    WRITE CLOCK
    WEN
    WCLK
    IR
    DATA IN
    RCLK
    READ CLOCK
    RCLK
    REN
    OE OUTPUT ENABLE
    OUTPUT READY
    Qn
    Dn
    IR
    GND
    WEN
    WCLK
    OR
    REN
    OE
    Qn
    READ ENABLE
    OR
    DATA OUT
    TRANSFER CLOCK
    4294 drw 31
    n
    RXI
    HF
    72V205
    72V215
    72V225
    72V235
    72V245
    WXI
    FL
    VCC
    GND
    (0,1)
    72V205
    72V215
    72V225
    72V235
    72V245
    RXI
    WXI
    FL
    VCC
    GND
    (0,1)
    PAF
    HF
    PAE
    n
    DEPTH EXPANSION CONFIGURATION (FWFT MODE)
    In FWFT mode, the FIFOs can be connected in series (the data outputs of
    one FIFO connected to the data inputs of the next) with no external logic
    necessary. Theresultingconfigurationprovidesatotaldepthequivalenttothe
    sumofthedepthsassociatedwitheachsingleFIFO. Figure31showsadepth
    expansionusingtwoIDT72V205/72V215/72V225/72V235/72V245devices.
    CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
    in the depth expansion configuration. The first word written to an empty
    configuration will pass from one FIFO to the next (“ripple down”) until it finally
    appears at the outputs of the last FIFO in the chain–no read operation is
    necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
    word appears at the outputs of one FIFO, that device’s OR line goes LOW,
    enabling a write to the next FIFO in line.
    Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
    thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO’s
    outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
    for each individual FIFO:
    (N – 1)*(4*transfer clock) + 3*TRCLK
    whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
    Note that extra cycles should be added for the possibility that the tSKEW1
    specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
    clock,fortheORflag.
    The“rippledown”delayisonlynoticeableforthefirstwordwrittentoanempty
    depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
    wordswrittentotheconfiguration.
    The first free location created by reading from a full depth expansion
    configurationwill“bubbleup”fromthelastFIFOtothepreviousoneuntilitfinally
    movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
    FIFOofthechain,thatFIFO’sIRlinegoesLOW,enablingtheprecedingFIFO
    to write a word to fill it.
    Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
    FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
    the sum of the delays for each individual FIFO:
    (N – 1)*(3*transfer clock) + 2 TWCLK
    where N is the number of FIFOs in the expansion and TWCLK is the WCLK
    period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
    specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
    clock, for the IRflag.
    TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
    isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
    end of the chain and free locations to the beginning of the chain.
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