IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 1" />
參數(shù)資料
型號(hào): IDT72V235L10TF8
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 16/25頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 2048X18 10NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 72V
功能: 同步
存儲(chǔ)容量: 36.8K(2K x 18)
數(shù)據(jù)速率: 100MHz
訪(fǎng)問(wèn)時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V235L10TF8
23
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
MARCH 2013
Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN
DATA OUT
RESET
IDT
72V205
72V215
72V225
72V235
72V245
WXO
WXI
RXO
RXI
FIRST LOAD (
FL)
FL
Vcc
WXO
WXI
RXO
RXI
WXO
WXI
RXO
RXI
IDT
72V205
72V215
72V225
72V235
72V245
IDT
72V205
72V215
72V225
72V235
72V245
FF/IR
PAF
EF/OR
PAE
FF/IR
PAF
EF/OR
PAE
FF/IR
PAF
EF/OR
PAE
EF/OR
PAE
FF/IR
PAF
4294 drw 30
RCLK
REN
OE
WCLK
WEN
RS
FL
RCLK
REN
OE
WCLK
WEN
RS
RCLK
REN
OE
WCLK
WEN
RS
LD
Dn
Qn
Dn
Qn
Dn
Qn
LD
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
Expansion using three IDT72V205/72V215/72V225/72V235/72V245s.
Maximumdepthislimitedonlybysignalloading.
Followthesesteps:
1. The first device must be designated by grounding the First Load (FL)
control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to
the Write Expansion In (WXI) pin of the next device. See Figure 30.
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 30.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
thepartialflagsareinasynchronoustimingmode.
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