IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
參數(shù)資料
型號： IDT72V243L7-5PF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 27/45頁
文件大?。?/td> 0K
描述： IC FIFO 2048X18 7-5NS 80QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 異步，同步
存儲容量： 36.8K（2K x 18）
數(shù)據(jù)速率： 133MHz
訪問時間： 5ns
電源電壓： 3.15 V ~ 3.45 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 72V243L7-5PF8
33
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
tENH
WEN
PAF
RCLK
tPAFS
REN
4666 drw21
tENS
tENH
tENS
tPAFS
D - m words in FIFO
(2)
tSKEW2(3)
1
2
12
D-(m+1) words
in FIFO
(2)
D-(m+1) words in FIFO
(2)
tCLKL
tCLKH
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
LD
WEN
D0 - D16
4666 drw19
tLDS
tENS
PAE OFFSET (LSB)
tDS
tDH
tLDH
tENH
tCLK
tCLKH
tCLKL
PAE OFFSET (MSB)
PAF OFFSET (LSB)
PAF OFFSET (MSB)
tDH
tDS
tLDH
tENH
RCLK
LD
REN
Q0 - Q16
tLDH
tLDS
tENS
DATA IN OUTPUT
REGISTER
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
tENH
4666 drw20
tCLK
tA
tCLKH
tCLKL
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
tA
tLDH
tENH
tA
NOTE:
1. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the
PAE offset and PAF offset for x9 bus width.
NOTES:
1.
OE = LOW.
2. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the
PAE offset and PAF offset for x9 bus width.
NOTES:
1. m =
PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283
and 131,072 for the IDT72V293.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193
for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073
for the IDT72V293.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V243L7-5PFGI 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 2048X18 7-5NS 80QFP
IDT72V243L7-5PFGI8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 2048X18 7-5NS 80QFP
IDT72V243L7-5PFI 功能描述:IC FIFO 2048X18 7-5NS 80QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V245L10PF 功能描述:IC FIFO SYNC 4KX18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V245L10PF8 功能描述:IC FIFO SYNC 4KX18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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