參數(shù)資料
型號(hào): IDT72V255LA15TFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 12/27頁(yè)
文件大小: 0K
描述: IC FIFO SS 8192X18 15NS 64-STQFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 72V
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
訪問(wèn)時(shí)間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72V255LA15TFI8
2
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO
8,192 x 18, 16,384 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
PIN CONFIGURATIONS
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC(1)
VCC
GND
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Q17
Q16
GND
Q15
Q14
VCC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
WCLK
PRS
MRS
LD
FWFT/SI
GND
FF
/IR
PAF
HF
V
CC
PAE
EF
/OR
RCLK
REN
RT
OE
Q5
Q4
V
CC
Q3
Q2
GND
Q1
Q0
GND
D0
D1
D2
D3
D4
D5
D6
4672 drw 02
The period required by the retransmit operation is now fixed and short.
The first word data latency period, from the time the first word is written to
anemptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync
family.)
SuperSync FIFOs are particularly appropriate for networking, video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
buffer large amounts of data.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(
WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (
REN) input. Data is read from the FIFO on every rising
edgeofRCLKwhen
RENisasserted. AnOutputEnable(OE)inputisprovided
for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
NOTE:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
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