參數(shù)資料
型號(hào): IDT72V261LA10TF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 27/27頁
文件大?。?/td> 0K
描述: IC FIFO SS 8192X18 10NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 72V
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
數(shù)據(jù)速率: 100MHz
訪問時(shí)間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72V261LA10TF8
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 30, 2009
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
EMPTY OFFSET (LSB) REG.
87
0
EMPTY OFFSET (MSB) REG.
00H
85
0
FULL OFFSET (LSB) REG.
87
0
FULL OFFSET (MSB) REG.
00H
8
5
0
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
8
7
0
EMPTY OFFSET (MSB) REG.
00H
8
6
0
4673 drw 06
FULL OFFSET (LSB) REG.
8
7
0
FULL OFFSET (MSB) REG.
00H
8
6
0
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
IDT72V261LA
16,384 x 9 BIT
IDT72V271LA
32,768 x 9 BIT
WCLK
RCLK
Selection
X
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
No Operation
X
Write Memory
X
Read Memory
X
No Operation
4673 drw 07
LD
0
X
1
0
WEN
0
1
0
X
1
REN
1
0
1
X
0
1
X
Serial shift into registers:
28 bits for the 72V261LA
SEN
1
X
0
30 bits for the 72V271LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
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