參數(shù)資料
型號： IDT72V261LA15TF8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 6/27頁
文件大小： 0K
描述： IC FIFO SS 8192X18 15NS 64QFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 72V
功能： 同步
存儲容量： 144K（8K x 18）
數(shù)據(jù)速率： 67MHz
訪問時間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 72V261LA15TF8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
14
JANUARY 30, 2009
FWFT mode, the total number of writes necessary to deassert
IR is one
greater than needed to assert
FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/
IR are double register-buffered outputs.
EMPTY FLAG (
EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty
Flag (
EF) function is selected. When the FIFO is empty, EF will go
LOW, inhibiting further read operations. When
EF is HIGH, the FIFO is
not empty. See Figure 8, Read Cycle, Empty Flag and First Word
Latency Timing (IDT Standard Mode), for the relevant timing informa-
tion.
In FWFT mode, the Output Ready (
OR) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs.
OR stays LOW after the RCLK LOW to
HIGH transition that shifts the last word from the FIFO memory to the
outputs.
OR goes HIGH only with a true read (RCLK with REN =
LOW). The previous data stays at the outputs, indicating the last word
was read. Further data reads are inhibited until
OR goes LOW again.
See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In
FWFT mode,
OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the
FIFO reaches the almost-full condition. In IDT Standard mode, if no
reads are performed after reset (
MRS), PAF will go LOW after (D - m)
words are written to the FIFO. The
PAF will go LOW after (16,384-m)
writes for the IDT72V261LA and (32,768-m) writes for the IDT72V271LA.
The offset “m” is the full offset value. The default setting for this value is
stated in the footnote of Table 1.
In FWFT mode, the
PAF will go LOW after (16,385-m) writes for
the IDT72V261LA and (32,769-m) writes for the IDT72V271LA, where
m is the full offset value. The default setting for this value is stated in
the footnote of Table 2.
See Figure 16, Programmable Almost-Full Flag Timing (IDT Stan-
dard and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE) will go LOW when the
FIFO reaches the almost-empty condition. In IDT Standard mode,
PAE
will go LOW when there are n words or less in the FIFO. The offset “n”
is the empty offset value. The default setting for this value is stated in
the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or
less in the FIFO. The default setting for this value is stated in the
footnote of Table 2.
See Figure 17, Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
PAE is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills
the FIFO beyond half-full sets
HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or
equal to half of the total depth of the device; the rising RCLK edge that
accomplishes this condition sets
HF HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where
D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
In FWFT mode, if no reads are performed after reset (
MRS or PRS),
HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385
for the IDT72V261LA and 32,769 for the IDT72V271LA.
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HF is updated by both
RCLK and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Q8)
(Q0 - Q8) are data outputs for 9-bit wide data.
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IDT72V261LA20PF8 功能描述:IC FIFO SS 8192X18 20NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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