IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� IDT72V273L6BC
寤犲晢锛� IDT, Integrated Device Technology Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 12/45闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FIFO 16384X18 6NS 100BGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� 72V
鍔熻兘锛� 鍚屾
瀛樺劜(ch菙)瀹归噺锛� 288K锛�16K x 18锛�
鏁�(sh霉)鎿�(j霉)閫熺巼锛� 166MHz
瑷晱(w猫n)鏅�(sh铆)闁擄細 4ns
闆绘簮闆诲锛� 3.15 V ~ 3.45 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 100-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-CABGA锛�11x11锛�
鍖呰锛� 鎵樼洡
鍏跺畠鍚嶇ū锛� 72V273L6BC
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
DESCRIPTION:
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO)
memories with clocked read and write controls and a flexible Bus-Matching x9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:
Flexible x9/x18 Bus-Matching on both read and write ports
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
Asynchronous/Synchronous translation on the read or write ports
High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
PIN CONFIGURATIONS
TQFP (PN80-1, order code: PF)
TOP VIEW
DNC(1)
OE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
IW
GND
D17
D16
D14
D15
D13
GND
D12
D11
D10
D9
D8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
59
RT
Q17
Q16
GND
Q15
Q14
Q13
Q12
Q11
GND
Q9
Q8
Q7
INDEX
WEN
SEN
DNC(1)
Q10
VCC
4666 drw02
20
1
VCC
VCC
GND
VCC
VCC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
79
WCLK
PRS
MRS
LD
FWFT/SI
FF
/IR
PAF
OW
FSEL0
HF
FSEL1
BE
IP
V
CC
PAE
PFM
EF
/OR
RM
RCLK
REN
D7
D6
GND
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
GND
Q6
NOTE:
1. DNC = Do Not Connect.
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
IDT72V273L6PF 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜(ch菙)瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱(w猫n)鏅�(sh铆)闁�:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
IDT72V273L6PF8 鍔熻兘鎻忚堪:IC FIFO 16384X18 6NS 80QFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:7200 鍔熻兘:鍚屾 瀛樺劜(ch菙)瀹归噺:288K锛�16K x 18锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:100MHz 瑷晱(w猫n)鏅�(sh铆)闁�:10ns 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:64-LQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:64-TQFP锛�14x14锛� 鍖呰:鎵樼洡 鍏跺畠鍚嶇ū:72271LA10PF
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IDT72V273L7-5BC 鍔熻兘鎻忚堪:IC FIFO 16384X18 7-5NS 100BGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 閭忚集 - FIFO 绯诲垪:72V 妯�(bi膩o)婧�(zh菙n)鍖呰:15 绯诲垪:74F 鍔熻兘:鐣版 瀛樺劜(ch菙)瀹归噺:256锛�64 x 4锛� 鏁�(sh霉)鎿�(j霉)閫熺巼:- 瑷晱(w猫n)鏅�(sh铆)闁�:- 闆绘簮闆诲:4.5 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:閫氬瓟 灏佽/澶栨:24-DIP锛�0.300"锛�7.62mm锛� 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-PDIP 鍖呰:绠′欢 鍏跺畠鍚嶇ū:74F433
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