IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM 65,536 x 9 " />
參數(shù)資料
型號: IDT72V291L15TFI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/26頁
文件大?。?/td> 0K
描述: IC FIFO SS 32768X36 15NS 64QFP
標(biāo)準(zhǔn)包裝: 80
系列: 72V
功能: 同步
存儲容量: 1.1M(32K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V291L15TFI
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFOTM
65,536 x 9 and 131,072 x 9
NOTES:
1. m =
PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
In FWFT mode: D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
WCLK
tENS
tENH
WEN
HF
tENS
tHF
RCLK
tHF
REN
4513 drw 23
tCLKL
tCLKH
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
D/2 + 1 words in FIFO
(1),
[
+ 2
] words in FIFO(2)
D-1
2
D/2 words in FIFO(1),
[
+ 1
] words in FIFO(2)
D-1
2
WCLK
t ENH
t CLKH
tCLKL
WEN
PAE
RCLK
t ENS
n words in FIFO (2),
n+1 words in FIFO (3)
tPAE
tSKEW2
tPAE
12
(4)
REN
4513 drw 22
t ENS
t ENH
n+1 words in FIFO (2),
n+2 words in FIFO (3)
n words in FIFO (2),
n+1 words in FIFO (3)
WCLK
t ENH
t CLKH
tCLKL
WEN
PAF
RCLK
(3)
tPAF
REN
4513 drw 21
t ENS
t ENH
t ENS
D - (m+1) words in FIFO(2)
tPAF
D - m words in FIFO(2)
tSKEW2
1
2
12
D-(m+1) words
in FIFO(2)
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