IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS" />
參數(shù)資料
型號(hào)： IDT72V3634L15PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 23/34頁(yè)
文件大小： 0K
描述： IC FIFO 512X36X2 15NS 128QFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 36.8K（512 x 36 x 2）
數(shù)據(jù)速率： 67MHz
訪問時(shí)間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3634L15PF8
3
COMMERCIALTEMPERATURERANGE
IDT72V3624/72V3634/72V3644 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox
registers. The mailbox registers’ width matches the selected Port B bus width.
Each Mailbox register has a flag (
MBF1 and MBF2) to signal when new mail
has been stored.
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial
Reset.MasterResetinitializesthereadandwritepointerstothefirstlocationof
the memory array, configures the FIFO for Big- or Little-Endian byte arrange-
ment and selects serial flag programming, parallel flag programming, or one of
threepossibledefaultflagoffsetsettings,8,16or64.TherearetwoMasterReset
pins,
MRS1 and MRS2.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong-
word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation is required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFTpin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).
The
EFandFFfunctionsareselectedintheIDTStandardmode.EFindicates
whether or not the FIFO memory is empty.
FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEAandAEB)and
aprogrammableAlmost-Fullflag(
AFAandAFB). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory.
AFAandAFBindicate
when the FIFO contains more than a selected number of words.
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport
clockthatwritesdataintoitsarray.
EFA/ORA,EFB/ORB,AEAandAEBaretwo-
stage synchronized to the port clock that reads data from its array. Program-
mable offsets for
AEA, AEB, AFA and AFB areloaded inparallelusingPortA
or in serial via the SD input. The Serial Programming Mode pin (
SPM) makes
thisselection.Threedefaultoffsetsettingsarealsoprovided.The
AEAandAEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary.
AllthesechoicesaremadeusingtheFS0andFS1inputsduringMasterReset.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V3624/72V3634/72V3644 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available. They
are fabricated using IDT’s high speed, submicron CMOS technology.
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