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參數資料
| 型號： | IDT72V3640L6PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 14/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SS 1024X36 6NS 128-TQFP |
| 標準包裝： | 1,000 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 36.8K（1K x 36） |
| 數據速率： | 166MHz |
| 訪問時間： | 4ns |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3640L6PF8 |
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21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
BIG-ENDIAN/LITTLE-ENDIAN (
BE )
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BEduringMasterResetwillselectLittle-Endianformat.Thisfunction
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (
BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable
flag timing mode. If asynchronous
PAF/PAE configuration is selected (PFM,
LOW during
MRS),thePAEisassertedLOWontheLOW-to-HIGHtransition
of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly,the
PAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
written to and read from the FIFO.
OUTPUTS:
FULL FLAG (
FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (
FF) function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the
IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and
32,768 for the IDT72V3690. See Figure 7, Write Cycle and Full Flag Timing
(IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
to the FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097
for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680
and 32,769 for the IDT72V3690. See Figure 9, Write Timing (FWFT Mode),
for the relevant timing information.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
double register-buffered outputs.
EMPTY FLAG (
EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
functionisselected. WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurther
read operations. When
EFisHIGH,theFIFOisnotempty.SeeFigure8,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs.
OR goes HIGH only with
a true read (RCLK with
REN = LOW). The previous data stays at the outputs,
indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
ORgoes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAFwillgoLOWafter(D - m)wordsarewritten
to the FIFO. The
PAFwillgoLOWafter(1,024-m)writesfortheIDT72V3640,
(2,048-m) writes for the IDT72V3650, (4,096-m) writes for the IDT72V3660,
(8,192-m) writes for the IDT72V3670, (16,384-m) writes for the IDT72V3680
and(32,768-m)writesfortheIDT72V3690.Theoffset“m”isthefulloffsetvalue.
The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAF will go LOW after (1,025-m) writes for the
IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m) writes for the
IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m) writes for
the IDT72V3680 and (32,769-m) writes for the IDT72V3690, where m is the
full offset value. The default setting for this value is stated in Table 2.
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAF configurationisselected,thePAF isassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). Ifsynchronous
PAF
configuration is selected, the
PAFisupdatedontherisingedgeofWCLK. See
Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode,
PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
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| IDT72V3640L7-5PF | 功能描述:IC FIFO SS 1024X36 7-5NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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