IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM
參數(shù)資料
型號: IDT72V3650L7-5BB8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 23/46頁
文件大?。?/td> 0K
描述: IC FIFO SS 2048X36 7-5NS 144BGA
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 72K(2K x 36)
數(shù)據(jù)速率: 133MHz
訪問時間: 5ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-BGA
供應(yīng)商設(shè)備封裝: 144-PBGA(13x13)
包裝: 帶卷 (TR)
其它名稱: 72V3650L7-5BB8
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
OCTOBER 22, 2008
PIN CONFIGURATIONS (CONTINUED)
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
ASYW
WEN
WCLK
PAF
FF/IR
HF
BM
EF
RCLK
REN
OE
Q35
SEN
IW
PRS
LD
MRS
FS0
FS1
ASYR
IP
PFM
RT
Q34
D35
D34
D33
FWFT/SI
OW
VCC
BE
PAE
RM
Q32
Q3
3
D32
D31
D30
VCC
GND
VCC
Q29
Q30
Q31
D29
D26
D27
VCC
Q26
Q27
Q28
D28
D25
D24
Q23
Q24
Q25
D21
D22
D23
Q22
Q21
Q20
D18
D19
D20
VCC
Q19
Q18
Q17
D15
D16
D17
VCC
Q16
Q15
Q14
D12
D13
D14
D3
D0
VCC
TDO
Q2
Q13
Q12
Q11
D10
D6
D4
D1
TMS
TCK
Q0
Q3
Q5
Q10
Q9
D8
D7
D5
D2
TRST
TDI
Q1
Q4
Q6
Q7
Q8
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
12
3
4
5
6
7
8
9
10
11
12
4667 drw02b
GND
VCC
GND
VCC
GND
VCC
GND
D11
D9
VCC
WCLK when
WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN input should be tied to its active state, (LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (
REN)input. Data
is read from the FIFO on every rising edge of RCLK when
REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN input should be tied to its
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
the FIFO must be configured for Standard IDT mode, and the
OE input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
RENandenablingarisingRCLKedge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
RENdoes
not have to be asserted for accessing the first word. However, subsequent
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IDT72V3650L7-5PFI 功能描述:IC FIFO SS 2048X36 7-5NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K(16K x 18) 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP(14x14) 包裝:托盤 其它名稱:72271LA10PF
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