IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x " />
參數(shù)資料
型號(hào): IDT72V3652L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 12/29頁(yè)
文件大小: 0K
描述: IC BI FIFO 4096X36 15NS 120QFP
標(biāo)準(zhǔn)包裝: 750
系列: 72V
功能: 異步,同步
存儲(chǔ)容量: 147K(4K x 36)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 3.15 V ~ 3.45 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱(chēng): 72V3652L15PF8
2
COMMERCIALTEMPERATURERANGE
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FEBRUARY 4, 2009
DESCRIPTION (CONTINUED)
NOTES:
1. Electrical pin 1 in center of beveled edge.
2. NC – no internal connection
3. Uses Yamaichi socket IC51-1324-828
PQFP(3) (PQ132-1, order code: PQF)
TOP VIEW
NC
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
FWFT
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
4660 drw02
NC
VCC
CLKB
ENB
W
/R
B
CSB GND
AFB
AEB VCC
MBF1
MBB
RST2
FS1
GND
FS0
RST1
MBA
MBF2
AEA AFA
VCC
EFA
/ORA
FFA
/IRA
CSA
W/
R
A
ENA
CLKA
GND
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
B
11
B
10
B
9
B
7
B
8
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
74
76
77
78
79
80
81
82
83
75
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
FFB
/IRB
EFB
/ORB
support clock frequencies up to 100MHz and have read access times as fast
as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs
onboardeachchipbufferdatainoppositedirections.Communicationbetween
eachportmaybypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailbox
register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the
FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The
EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty.
FF shows whether the
PIN CONFIGURATION
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