參數(shù)資料
型號(hào)： IDT72V71623DAG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 0K
描述： IC DGTL SW 2048X2048 144-TQFP
標(biāo)準(zhǔn)包裝： 30
系列： 72V
類(lèi)型： 多路復(fù)用器
電路： 1 x 1:16
獨(dú)立電路： 1
電壓電源： 單電源
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
其它名稱(chēng)： 72V71623DAG
6
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
evaluationstarts.Twoframeslater,thecompleteframeevaluation(CFE)bitof
theframealignmentregister(FAR)changesfromlowtohightosignalthatavalid
offsetmeasurementisreadytobereadfrombits0to11oftheFARregister.The
SFE bit must be set to zero before a new measurement cycle is started.
InST-BUSmode,thefallingedgeoftheframemeasurementsignal(FE)
isevaluatedagainstthefallingedgeoftheST-BUSframepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 6 and Figure 5 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
TheIDT72V71623providesuserswiththecapabilityofinitializingtheentire
ConnectionMemoryblockintwoframes.Tosetbits15to13ofeveryConnection
Memory location, first program the desired pattern in bits 9 to 7 of the Control
Register.
Setting the memory block program (MBP) bit of the control register high
enablestheblockprogrammingmode.Whentheblockprogrammingenable
(BPE)bitoftheControlRegisterissettohigh,theblockprogrammingdatawill
beloadedintothebits15to13ofeveryConnectionMemorylocation.Theother
ConnectionMemorybits(bit12tobit0)areloadedwithzeros.Whenthememory
blockprogrammingiscomplete,thedeviceresetstheBPEbittozero.
LOOPBACKCONTROL
Theloopbackcontrol(LPBK)bitofeachConnectionMemorylocationallows
theTXoutputdatatobeloopedbackedinternallytotheRXinputfordiagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delayoffsetregistersmustbesettozeroandthedevicemustbeinregularswitch
mode (DR3-0 = 0x0, 0x1 or 0x2).
DELAY THROUGH THE IDT72V71623
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesonaper-channelbasis.Forvoiceapplications,Variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,Constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
The delay through the device varies according to the type of throughput
delay selected in the MOD1 and MOD0 bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0x0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination serial stream speed. Although the minimum delay achievable is
dependent on the input and output serial stream speed, if data is switched
out+3channelsoftheslowestdatarate,thedatawillbeswitchedoutinthesame
frameexceptiftheinputandoutputdataratesareboth16Mb/s(DR3-0=0x3).
(See Figure 2 for example).
Forexample,giventheinputdatarateis2Mb/sandtheoutputdatarateis
8Mb/s,inputchannelCH0 canbeswitchoutbyoutputchannelCH12. Inthe
aboveexampletheinputstreamsareslowerthantheoutputstreams. Also,for
every2Mb/stimeslottherearefour8Mb/stimeslots,thusathree2Mb/schannel
delayequatesto12outputchanneltimeslots.SeeFigure2forthisexampleand
otherexamplesofminimumdelaytoguaranteetransmissioninthesameframe.
CONSTANT DELAY MODE (MOD1-0 = 0x1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipleDataMemorybuffer.Inputchanneldataiswritteninto
the Data Memory buffers during frame n will be read out during frame n+2.
Figure 1 shows examples of Constant Delay mode.
MICROPROCESSORINTERFACE
TheIDT72V71623’smicroprocessorinterfacelookslikeastandardRAM
interfacetoimproveintegrationintoasystem.Witha14-bitaddressbusanda
16-bitdatabus,readandwritesaremappeddirectlyintoDataandConnection
memoriesandrequireonlyoneMasterClockcycletoaccess.Byallowingthe
internal memories to be randomly accessed in one cycle, the controlling
microprocessor has more time to manage other peripheral devices and can
moreeasilyandquicklygatherinformationandsetuptheswitchpaths.
Table2showsthemappingoftheaddressesintointernalmemoryblocks,
Table 3 shows the Control Register information and Figure 11 and Figure 12
showsasynchronousandsynchronousmicroprocessoraccesses.
MEMORYMAPPING
The address bus on the microprocessor interface selects the internal
registersandmemoriesoftheIDT72V71623.Thetwomostsignificantbitsofthe
addressselectbetweentheregisters,DataMemory,andConnectionMemory.
IfA13andA12areHIGH,A11-A0areusedtoaddresstheDataMemory(Read
Only)wheredataoutputisreadfromthe8leastsignificantbitsonthedatabus.
If A13 is HIGH and A12 is LOW, A11-A0 are used to address Connection
Memory(Read/Write).IfA13isLOWandA12isHIGHA11-A9areusedtoselect
theControlRegister,FrameAlignmentRegister,andFrameOffsetRegisters.
See Table 2 for mappings..
CONTROL REGISTER
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigura-
tions sections, after system power-up, the Control Register should be pro-
grammedimmediatelytoestablishthedesiredswitchingconfiguration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit(MBP),theBlockProgrammingData(BPD)bits,theBeginBlockProgram-
mingEnable(BPE),theOutputStandBy(OSB),StartFrameEvaluation(SFE),
and Data Rate Select bits (DR 3-0). As explained in the Memory Block
Programmingsection,theBPEbeginstheprogrammingiftheMBPbitisenabled.
This allows the entire Connection Memory block to be programmed with the
BlockProgrammingDatabits.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the MOD1-0 bits of each Connection
Memory location controls the output drivers. See Table 1 for detail. The
Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the
ConnectionMemory.InProcessorChannelMode,thisallowsthemicroproces-
sor to access TX output channels. Once the MOD1-0 bits are set the lower 8
bits of the Connection Memory will be output on the TX serial streams. Also
controlledintheConnectionMemoryistheVariableDelaymodeorConstant
Delay mode. Each Connection Memory location allows the per-channel
selection between Variable and Constant throughput Delay modes and
Processormode.
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