IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, D" />
參數(shù)資料
型號(hào)： IDT72V801L10PF8
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 0K
描述： IC SYNC FIFO 256X9 10NS 64QFP
標(biāo)準(zhǔn)包裝： 750
系列： 72V
功能： 異步
存儲(chǔ)容量： 2.3K（256 x 9）
數(shù)據(jù)速率： 100MHz
訪(fǎng)問(wèn)時(shí)間： 10ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱(chēng)： 72V801L10PF8
8
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
OUTPUTS
OUTPUTS:::::
Full Flag (
FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA(FFB) will go LOW after 256 writes to the IDT72V801's FIFO A (B), 512
writes to the IDT72V811's FIFO A (B), 1,024 writes to the IDT72V821's FIFO
A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the
IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B).
FFA(FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB).
Empty Flag (
EFA, EFB) — EFA(EFB) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA(EFB) is synchronized with respect to the LOW-to-HIGH transition of
the Read Clock RCLKA (RCLKB).
Programmable Almost–Full Flag (
PAFA, PAFB) —PAFA(PAFB)willgo
LOW when the amount of data in Array A (B) reaches the Almost-Full condition.
If no reads are performed after reset,
PAFA(PAFB) will go LOW after (256-m)
writes to the IDT72V801's FIFO A (B), (512-m) writes to the IDT72V811's FIFO
A (B), (1,024-m) writes to the IDT72V821's FIFO A (B), (2,048-m) writes to
the IDT72V831's FIFO A (B), (4,096-m) writes to the IDT72V841's FIFO A
(B), or (8,1912-m) writes to the IDT72V851's FIFO A (B).
FFA(FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
Registers.
If there is no Full offset specified,
PAFA(PAFB)willgoLOWatFull-7words.
PAFA(PAFB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
of the Write Clock WCLKA (WCLKB).
Programmable Almost–Empty Flag (
PAEA,PAEB)—PAEA(PAEB)will
go LOW when the read pointer is "n+1" locations less than the write pointer.
Theoffset"n"isdefinedintheEmptyOffsetRegisters. Ifnoreadsareperformed
after reset,
PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
If there is no Empty offset specified,
PAEA(PAEB)willgoLOWatEmpty+7
words.
PAEA(PAEB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 – QA8, QB0 – QB8 ) — QA0 - QA8 are the nine data
outputs for memory array A, QB0 - QB8 are the nine data outputs for memory
array B.
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
IDT72V801
IDT72V811
IDT72V821
00
0
H
L
1 to n(1)
HH
L
H
(n+1) to (256-(m+1))
(n+1) to (512-(m+1))
(n+1) to (1,024-(m+1))
HHHH
(256-m)(2) to 255
(512-m)(2) to 511
(1,024-m)(2) to 1,023
H
L
H
256
512
1,024
L
H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
NUMBER OF WORDS IN ARRAY A
FFA
PAFA
PAEA
EFA
NUMBER OF WORDS IN ARRAY B
FFB
PAFB
PAEB
EFB
IDT72V831
IDT72V841
IDT72V851
000
H
L
1 to n(1)
HH
L
H
(n+1) to (2,048-(m+1))
(n+1) to (4,096-(m+1))
(n+1) to (8,192-(m+1))
HHHH
(2,048-m)(2) to 2,047
(4,096-m)(2) to 4,095
(8,192-m)(2) to 8,191
H
L
H
2,048
4,096
8,192
L
H
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
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