IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM DUAL 256 x 9, DUAL 512 x 9, D" />
參數(shù)資料
型號: IDT72V811L20TF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/16頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 512X9 20NS 64QFP
標(biāo)準(zhǔn)包裝: 80
系列: 72V
功能: 異步
存儲容量: 4.6K(512 x 9)
數(shù)據(jù)速率: 50MHz
訪問時(shí)間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 72V811L20TF
5
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
OutputLoad
See Figure 1
Commercial
Com’l & Ind’l
Commercial
IDT72V801L10
IDT72V801L15
IDT72V801L20
IDT72V811L10
IDT72V811L15
IDT72V811L20
IDT72V821L10
IDT72V821L15
IDT72V821L20
IDT72V831L10
IDT72V831L15
IDT72V831L20
IDT72V841L10
IDT72V841L15
IDT72V841L20
IDT72V851L10
IDT72V851L15
IDT72V851L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
100
66.7
50
MHz
tA
Data Access Time
2
6.5
2
10
2
12
ns
tCLK
Clock Cycle Time
10
15(1)
—20
ns
tCLKH
Clock High Time
4.5
6
8
ns
tCLKL
Clock Low Time
4.5
6
8
ns
tDS
Data Set-up Time
3
4
5
ns
tDH
Data Hold Time
0.5
1
1
ns
tENS
Enable Set-up Time
3
4
5
ns
tENH
Enable Hold Time
0.5
1
1
ns
tRS
Reset Pulse Width(2)
10
15
20
ns
tRSS
Reset Set-up Time
8
10
12
ns
tRSR
Reset Recovery Time
8
10
12
ns
tRSF
Reset to Flag Time and Output Time
10
15
20
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—
0
0—
ns
tOE
Output Enable to Output Valid
3
6
3
8
3
10
ns
tOHZ
Output Enable to Output in High-Z(3)
363
8
3
10
ns
tWFF
Write Clock to Full Flag
6.5
10
12
ns
tREF
Read Clock to Empty Flag
6.5
10
12
ns
tPAF
Write Clock to Programmable Almost-Full Flag
6.5
10
12
ns
tPAE
Read Clock to Programmable Almost-Empty Flag
6.5
10
12
ns
tSKEW1
Skew Time Between Read Clock and Write Clock
5
6
8
ns
for Empty Flag and Full Flag
tSKEW2
Skew Time Between Read Clock and Write Clock for
14
18
20
ns
Programmable Almost-Empty Flag and Programmable
Almost-Full Flag
*Includes jig and scope capacitances.
Figure 1. Output Load
or equivalent circuit
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
30pF*
330
3.3V
510
D.U.T.
4093 drw 03
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0
°C to +70°C; Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
AC TEST CONDITIONS
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