參數(shù)資料
型號: IDT72V835L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/26頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 2048X18 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 36.8K(2K x 18)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V835L15PF8
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
23
FEBRUARY 11, 2009
Figure 29. Block Diagram of the Two FIFOs Contained in One IDT72V805/72V815/72V825/72V835/72V845
Configured for a 36-Bit Width Expansion
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG/INPUT
READY (FF/IR)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
EMPTY FLAG/OUTPUT
READY (EF/OR)
PROGRAMMABLE (PAF)
RESET (RS)
FIFO A
FIFO B
RESET (RS)
36
18
FF/IR
EF/OR
4295 drw 29
FL
WXI RXI
FL
WXI RXI
FF/IR
EF/OR
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
RESET (RS)
IDT
72V805
72V815
72V825
72V835
72V845
4295 drw 28
FL
RXI
WXI
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72V805/72V815/
72V825/72V835/72V845 may be used as a stand-alone device when the
application requirements are for 256/512/1,024/2,048/4,096 words or less.
These FIFOs are in a single Device Configuration when the First Load (
FL),
Write Expansion In (
WXI) and Read Expansion In (RXI) control inputs are
configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(one of the two FIFOs contained in the IDT72V805/72V815/72V825/72V835/72V845)
NOTE:
1. Do not connect any output control signals directly together.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two
IDT72V805/72V815/72V825/72V835/72V845s. Any word width can be
attainedbyaddingadditionalIDT72V805/72V815/72V825/72V835/72V845s.
These FIFOs are in a single Device Configuration when the First Load (
FL),
Write Expansion In (
WXI) and Read Expansion In (RXI) control inputs are
configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 29). Please see the Application Note AN-83.
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