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參數(shù)資料
| 型號： | IDT73720AJ8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | 73 SERIES, 16-BIT EXCHANGER, TRUE OUTPUT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IDT73720AJ8 |
1
COMMERCIALTEMPERATURERANGE
IDT73720/A
16-BIT TRI-PORT BUS EXCHANGER
DECEMBER 1999
1999
Integrated Device Technology, Inc.
DSC-2527/7
c
IDT73720/A
COMMERCIAL TEMPERATURE RANGE
16-BIT TRI-PORT
BUS EXCHANGER
FUNCTIONAL BLOCK DIAGRAM
Y-W RITE
LATCH
BUS CON TROL
PATH
LEX Y
LEY X
(Even Path)
LEZX
16
8
OEYL
OEYU
88
M
U
X
16
OEXL
OEXU
16
OEXU
Y0:7
Y8:15
X0:7
X8:15
Y-R EAD
LATCH
16
88
16
OEXL
OEYU
OEYL
OEZU
OEZL
Z-READ
LATCH
88
16
T/R
OEU
OEL
Z-W R ITE
LATCH
LEXZ
(Odd Path)
16
8
OEZL
OEZU
88
Z0:7
Z8:15
16
8
FEATURES:
– High-speed 16-bit bus exchange for interbus communication in the
followingenvironments:
Multi-way interleaving memory
Multiplexed address and data buses
– Direct interface to R3051 family RISChipSet
R3051 family of integrated RISController CPUs
R3721 DRAM controller
– Data path for read and write operations
– Low noise 12mA TTL level outputs
– Bidirectional 3-bus architecture: X, Y, Z
One CPU bus: X
Two (interleaved or banked) memory buses:Y & Z
Each bus can be independently latched
– Byte control on all three buses
– Source terminated outputs for low noise and undershoot control
– 68-pin PLCC and 80-pin PQFP package
– High-performance CMOS technology.
DESCRIPTION:
The IDT73720/A Bus Exchanger is a high speed 16-bit bus exchange
deviceintendedforinter-buscommunicationininterleavedmemorysystems
and high performance multiplexed address and data buses.
The Bus Exchanger is responsible for interfacing between the CPU A/
D bus (CPU address/data bus) and multiple memory data buses.
The 73720/A uses a three bus architecture (X, Y, Z), with control signals
suitable for simple transfer between the CPU bus (X) and either memory bus
(Y or Z). The Bus Exchanger features independent read and write latches
for each memory bus, thus supporting a variety of memory strategies. All
three ports support byte enable to independently enable upper and lower
bytes.
NOTE:
1. Logic equations for bus control:
OEXU = T/
R* . OEU*; OEXL = T/R* . OEL*; OEYU = T/R. PATH . OEU*
OEYL = T/
R. PATH . OEL*; OEZU = T/R . PATH* . OEU*; OEZL = T/R . PATH* . OEL*
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