參數(shù)資料
型號(hào)： IDT7381L30J8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 位片處理器
英文描述： 16-BIT, BIT-SLICE MICROPROCESSOR, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 2/17頁(yè)
文件大?。?/td> 257K
代理商： IDT7381L30J8
10
COMMERCIALTEMPERATURERANGE
IDT7381
16-BIT CASCADABLE ALU
PROPAGATION DELAY CALCULATIONS FOR TWO IDT7381S
NOTE:
1. Flags are
P, G, OVF, Z and C16.
To Output
To Set PUT Time
From Input
F0 – 15
Flags (1)
Relative to Clock (CLK)
FTAB = 0, FTF = 0
CLK
As in 16-bit case
(Clk → C16) + (C0 → flag)
. . . .
C0
. . . .
(C0 → C16) + (C0 → flag)
(C0 → C16) + (C0 set–up time)
I0 – 2, RS0 – 1
. . . .
(I0–2, RS0–1 → C16) + (C0 → flag)
(I0–2, RS0–1 → C16) + (C0 set–up time)
A0 – 15, B0 – 15
. . . .
As in 16-bit case
ENA, ENB,ENF
. . . .
As in 16-bit case
FTAB = 0, FTF = 1
CLK
(Clk → C16) + (C0 → F0–15)(Clk → C16) + (C0 → flag)
. . . .
C0
(C0 → C16) + (C0 → F0–15)(C0 → C16) + (C0 → flag)
(C0 → C16) + (C0 set–up time)
I0 – 2, RS0 – 1
(I0–2, RS0–1 → C16) + (C0 → F0–15)(I0–2, RS0–1 → C16) + (C0 → flag)
(I0–2, RS0–1 → C16) + (C0 set–up time)
A0 – 15, B0 – 15
. . . .
As in 16-bit case
ENA, ENB,ENF
. . . .
As in 16-bit case
FTAB = 1, FTF = 0
CLK
As in 16-bit case
. . . .
C0
. . . .
(C0 → C16) + (C0 → flag)
(C0 → C16) + (C0 set–up time)
I0 – 2, RS0 – 1
. . . .
(I0–2, RS0–1 → C16) + (C0 → flag)
(I0–2, RS0–1 → C16) + (C0 set–up time)
A0 – 15, B0 – 15
. . . .
(A0–15, B0–15 → C16) + (C0 → flag)
As in 16-bit case
ENA, ENB,ENF
. . . .
As in 16-bit case
FTAB = 0, FTF = 1
CLK
Don't care condition
. . . .
C0
(C0 → C16) + (C0 → F0–15)(C0 → C16) + (C0 → flag)
. . . .
I0 – 2, RS0 – 1
(I0–2, RS0–1 → C16) + (C0 → F0–15)(I0–2, RS0–1 → C16) + (C0 → flag)
. . . .
A0 – 15, B0 – 15
(A0–15, B0–15 → C16) + (C0 → F0–15)(A0–15, B0–15 → C16) + (C0 → flag)
. . . .
ENA, ENB,ENF
. . . .
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