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| 型號： | IDT7381L55J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 位片處理器 |
| 英文描述： | 16-BIT, BIT-SLICE MICROPROCESSOR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 257K |
| 代理商： | IDT7381L55J |
11
IDT7381
16-BIT CASCADABLE ALU
COMMERCIALTEMPERATURERANGE
CASCADING THE IDT7381
Some applications require 32-bit or wider input operands. Cascading
is the hardware solution. It provides a high speed alternative in handling
more than 16-bit wide operands.
1. Cascading the IDT7381
Cascading to 32-bit wide operands takes only two IDT7381s and no
external hardware. However, cascading to data widths greater than 32-
bit can be done in two ways: without external hardware (slow method) or
by using a carry look ahead generator.
a) Cascading the IDT7381 without a carry-look-ahead generator:
(Figures 1 and 2)
1. Connect the C16 output of the least significant device into the C0
input of the next most significant device.
2. Common lines to all devices are: RS0–1, I0–2, Clk, FTF, FTAB,
ENA, ENB, ENF.
3. Take OVF, C16,
P, G of the most significant device as valid.
4. The system’s zero flag (Z) is obtained by ANDing all zero flag
results.
b) Cascading three or more IDT7381s with carry-look-ahead (CLA)
generator: (Figure 3)
1. Connect the
PandGoutputsofeachdevicetotheCLAgenerator’s
corresponding inputs.
2. Take the CLA generator outputs into the C0 inputs of each device
(except for the least significant one).
3. Common lines to all devices are: RS0–1, I0–2, Clk, FTF, FTAB,
ENA, ENB, ENF.
4. Take OVF, C16,
P, G of the most significant device as valid.
5. Carry-in to the system should be connected to the C0 input of the
least significant device and also to the CLA generator.
2. Time Delay Considerations
Once cascading has taken place, time delays may become critical in high
performance systems. Our main interest here is focused on “propagation
delays”, i.e. calculating the time required for an input signal to propagate
through several cascaded devices up to a specific output in another device
within the cascaded system.
Propagation Delay
The propagation delay for two devices between the input and output of
interest (input to output delay) is done as follows:
1. Calculate delay between the input and C16 in the first device.
2. Calculate delay between C0 and the output in the second device.
3. Add both results.
The following table is an example on how to build a propagation delay
table for all inputs in a 32-bit IDT7381 cascaded system.
Propagation delay calculations can be extended to n–cascaded devices
as the sum of the delays in all devices between the input and output of interest.
That is:
(Input)1
→ (C16)1 = t1
...
(C0)i
→ (C16)i = ti
(C0)i + 1
→ (C16)i + 1 = ti + 1
...
(C0)n
→ (Output)n= tn
Where the subscript i denotes the device number and the arrow (
→)
represents the delay in between. Notice that i + 1 is the immediate upper
device from device i. Adding the delays ti we get:
Propagation delay = t1 + t2 + ... + ti + ti + 1 + ... + tn
Total Delay
As seen from Figure 8, the propagation delay is within the IDT7381
devices only. A complete analysis should also include the delay associated
with the transmission line Li (which depends on the line length and its
impedance). This line delay should then be added to the propagation delay
to obtain the total delay for the cascaded system:
Total delay = Propagation delay + Transmission line delay
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7383L25J | 制造商:Integrated Device Technology Inc 功能描述: 制造商:Integrated Device Technology Inc 功能描述:16-BIT, BIT-SLICE MICROPROCESSOR, PQCC68 |
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