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參數(shù)資料
| 型號(hào)： | IDT74ALVC16835PAG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 72K |
| 代理商： | IDT74ALVC16835PAG |
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
1
JANUARY 2004
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-4478/4
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
IDT74ALVC16835
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
DESCRIPTION:
This 18-bit universal bus driver is built using advanced dual metal
CMOS technology. Data flow from A to Y is controlled by the output-enable
(
OE) input. The device operates in the transparent mode when the latch-
enable (LE) input is high. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If LE is low, the A data is stored in the latch
flip-flop on the low-to-high transition of CLK. When
OE is high, the outputs
are in the high-impedance state.
The ALVC16835 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
LE
A1
TO 17 OTHER CHANNELS
OE
CLK
27
54
28
30
1
D
CLK
3
Y1
C1
APPLICATIONS:
SDRAM Modules
PC Motherboards
Workstations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74ALVC16835PA | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVC16835PA8 | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVC1G00DY8 | ALVC/VCX/A SERIES, 2-INPUT NAND GATE, PDSO5 |
| IDT74ALVCF162835PF8 | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| IDT74ALVCF162835PV8 | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74ALVC16835PFG | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動(dòng)器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVC16835PFG8 | 功能描述:IC UNIV BUS DVR 18BIT 56TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動(dòng)器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVC1G00DY | 制造商:INT_DEV_TECH 功能描述: |
| IDT74ALVCF162835APA | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動(dòng)器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74ALVCF162835APA8 | 功能描述:IC UNIV BUS DVR 18BIT 56TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74ALVCF 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動(dòng)器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
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