參數(shù)資料
型號: IDT74ALVCH16721PAG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC FLIP FLOP 20BIT 3ST 56-TSSOP
產(chǎn)品變化通告: Product Discontinuaton 29/Apr/2011
標(biāo)準(zhǔn)包裝: 34
系列: 74ALVCH
功能: 設(shè)置(預(yù)設(shè))和復(fù)位
類型: D 型
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個元件的位元數(shù): 20
頻率 - 時鐘: 150MHz
延遲時間 - 傳輸: 1ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 24mA,24mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: 74ALVCH16721PAG
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
1
JULY 2009
INDUSTRIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-4747/5
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Low switching noise
IDT74ALVCH16721
3.3V CMOS 20-BIT
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This20-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.The
20 flip-flops of the ALVCH16721 are edge-triggered D-type flip-flops with
qualified clock storage. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs if the clock-enable (
CLKEN)input
is low. If
CLKEN is high, no data is stored.
Abufferedoutput-enable(
OE)inputplacesthe20outputsineitheranormal
logicstate(highorlow)orahigh-impedancestate.Inthehigh-impedancestate,
the outputs neither load nor drive the bus lines significantly. The high-
impedance state and increased drive provide the capability to drive bus lines
withoutneedforinterfaceorpullupcomponents.
OEdoesnotaffecttheinternal
operationoftheflip-flops.Olddatacanberetainedornewdatacanbeentered
while the outputs are in the high-impedance state.
The ALVCH16721 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16721 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
CLK
OE
CLKEN
D1
1
56
29
55
CE
C1
1D
2
Q1
TO 19 OTHER CHANNELS
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