參數(shù)資料
型號: IDT74FCT162H272ATPF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通用總線功能
英文描述: FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
中文描述: FCT SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封裝: 0.40 MM PITCH, TVSOP-56
文件頁數(shù): 1/8頁
文件大小: 138K
代理商: IDT74FCT162H272ATPF
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.5
DSC-3071/3
1
IDT54/74FCT162H272AT/CT/ET
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST CMOS
12-BIT SYNCHRONOUS
BUS EXCHANGER
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
1
μ
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40
°
C to +85
°
C
Balanced Output Drivers:
±
24mA (commercial)
±
16mA (military)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25
°
C
Bus Hold retains last active bus state during 3-state
Eliminates the need for external pull up resistors
multiplexers for use in synchronous memory interleaving
applications. All registers have a common clock and use a
clock enable (
CE
xxx) on each data register to control data
sequencing. The output enables and mux select (
OEA
,
OEB
and SEL) are also under synchronous control allowing direc-
tion changes to be edge triggered events.
The tri-port bus exchanger has three 12-bit ports. Data may
be transferred between the A port and either/both of the B
ports. The clock enable (
CE1B
,
CE2B
,
CEA1B
and
CEA2B
)
inputs control the data storage. Both B ports have a common
output enable (
OEB
) to aid in synchronously loading the B
registers from the B port.
The FCT162H272AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times-reducing
the need for external series terminating resistors.
The FCT162H272AT/CT/ET have "Bus Hold" which re-
tains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
DESCRIPTION:
The FCT162H272AT/CT/ET synchronous tri-port bus ex-
changers are high-speed, bidirectional,12-bit, registered, bus
FUNCTIONAL BLOCK DIAGRAM
A-1B
REGISTER
CLK
SEL
OEB
OEA
12
M
U
X
12
12
A
1:12
1B
1:12
12
12
12
12
12
2B
1:12
CE1B
CEA1B
1
0
CE2B
CEA2B
1B-A
REGISTER
12
2B-A
REGISTER
A-2B
REGISTER
CONTROL
REGISTER
CE
D
Q
CE
D
Q
CE
D
Q
CE
D
Q
3071 drw 01
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