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參數(shù)資料
| 型號(hào)： | IDT74FCT163501APFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TVSOP-56 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | IDT74FCT163501APFG |
6
INDUSTRIALTEMPERATURERANGE
IDT74FCT163501A/C
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
Pulse
Generator
R T
D.U.T.
V CC
VIN
C L
VOUT
50pF
500
500
Open
GND
6v
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
SWITCH
GND
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3V
0V
1.5V
ENABLE
DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
6V
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT163501PA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT163501PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT163646PA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT163646PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT16373ATPA | 制造商:Integrated Device Technology Inc 功能描述:Latch, Dual, 8 Bit, 48 Pin, Plastic, TSSOP |
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