參數(shù)資料
型號(hào): IDT74FCT163827BPA
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 通用總線功能
英文描述: 3.3V CMOS 20-BIT BUFFERS
中文描述: FCT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: TSSOP-56
文件頁(yè)數(shù): 6/7頁(yè)
文件大?。?/td> 97K
代理商: IDT74FCT163827BPA
8.9
6
IDT74FCT163827A/B/C
FAST CMOS 20-BIT BUFFERS
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
3083 drw 05
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
3. If V
CC
is below 3V, input voltage swings should be adjusted not to
exceed V
CC
.
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Test
Switch
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
6V
GND
Open
3083 lnk 08
3083 drw 09
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
t
PZH
SWITCH
GND
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
GND
6V
Open
3083 drw 07
3083 drw 06
3083 drw 08
相關(guān)PDF資料
PDF描述
IDT74FCT163827BPF 3.3V CMOS 20-BIT BUFFERS
IDT74FCT163827BPV 3.3V CMOS 20-BIT BUFFERS
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IDT74FCT163951APF 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
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