參數(shù)資料
型號(hào): IDT74FCT163CTP
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 計(jì)數(shù)器
英文描述: FCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 5/7頁
文件大?。?/td> 157K
代理商: IDT74FCT163CTP
5
IDT54/74FCT163T/AT/CT
FASTCMOSSYNCHRONOUSPRESETTABLEBINARYCOUNTER
MILITARYANDCOMMERCIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163T
FCT163AT
FCT163CT
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
Symbol
Parameter
Condition(1)
Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max.
Unit
tPLH
tPHL
Propagation Delay
CP to Qn (
PE input HIGH)
CL = 50pF
RL = 500
2
11
2
11.5
2
7.2
2
7.5
2
5.8
2
6.3
ns
tPLH
tPHL
Propagation Delay
CP to Qn (
PE input LOW)
2
9.5
2
10
2
6.2
2
6.5
2
5.8
2
6.3
ns
tPLH
tPHL
Propagation Delay
CP to TC
2
15
2
16.5
2
9.8
2
10.8
2
7.4
2
8.3
ns
tPLH
tPHL
Propagation Delay
CET to TC
1.5
8.5
1.5
9
1.5
5.5
1.5
5.9
1.5
5.2
1.5
5.6
ns
tSU
Set-up Time HIGH or LOW
Pn to CP
5
5.5
4
4.5
4
4.5
ns
tH
Hold Time HIGH or LOW
Pn to CP
1.5
2
1.5
2
1.5
2
ns
tSU
Set-up Time HIGH or LOW
PE or SR to CP
11.5
13.5
9.5
11.5
9.5
11.5
ns
tH
Hold Time HIGH or LOW
PE or SR to CP
1.5
1.5
1.5
1.5
1.5
1.5
ns
tSU
Set-up Time HIGH or LOW
CEP ir CET to CP
11.5
13
9.5
11
9.5
11
ns
tH
Hold Time HIGH or LOW
CEP ir CET to CP
0—
0
0
0
0
0
ns
tW
CP Pulse Width (load)
HIGH or LOW
5—
5
4 (3)
4 (3)
4 (3)
4 (3)
—ns
tW
CP Pulse Width (count)
HIGH or LOW
7—
8
6
7
6
7
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
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