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參數(shù)資料
| 型號： | IDT74FCT2648ATP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| 中文描述： | FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 189K |
| 代理商： | IDT74FCT2648ATP |
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
3
FUNCTION TABLE (646/648)
FUNCTION TABLE (652)
Inputs
Data I/O
(1)
Operation or Function
G
DIR
X
X
L
L
H
H
CPAB
H or L
↑
X
X
X
H or L
CPBA
H or L
↑
X
H or L
X
X
SAB
X
X
X
X
L
H
SBA
X
X
L
H
X
X
A
1
- A
8
Input
B
1
- B
8
Input
FCT646T/FCT2646T
Isolation
Store A and B Data
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
FCT648T
H
H
L
L
L
L
Isolation
Store A and B Data
Real-Time
B
Data to A Bus
Stored
B
Data to A Bus
Real-Time
A
Data to B Bus
Stored
A
Data to B Bus
Output
Input
Input
Output
2634 tbl 02
Inputs
Data I/O
Operation or Function
GAB
L
L
X
H
GBA
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
X
(2)
SBA
X
X
X
X
A
1
- A
8
Input
B
1
- B
8
Input
FCT652T/FCT2652T
H
H
H
H
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers
Input
Input
Unspecified
(1)
Output
L
L
L
L
H
H
H
X
L
L
L
H
H
L
X
X
X
X
L
H
H
X
X
(2)
L
H
X
X
H
Unspecified
(1)
Output
Output
Input
Input
Input
Hold A, Store B
Store B in Both Registers
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and Stored B Data to A Bus
Input
Output
Output
Output
NOTES:
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = HIGH, L = LOW, X = Don't Care,
≠
= LOW-to-HIGH transition.
3.
A
in B Register.
4.
B
in A Register.
2634 tbl 03
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