參數(shù)資料
型號(hào)： IDT74FCT2652ATE
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： Ceramic Chip Capacitors / Standard Z5U; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: Z5U; Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: Unmarked
中文描述： FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP24
封裝： CERPACK-24
文件頁數(shù)： 7/9頁
文件大?。?/td> 189K
代理商： IDT74FCT2652ATE
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.20
7
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
2634 tbl 09
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. GAB,
GBA
to Bus for 652.
4. This parameter is guaranteed but not tested.
2634 tbl 10
646/648/652T
2646/2652T
Com'l.
646/648/652AT
2646/2652AT
Com'l.
Mil.
Mil.
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min.(2)
2.0
Max.
9.0
Min.(2)
2.0
Max.
11.0
Min.(2)
2.0
Max.
6.3
Min.(2)
2.0
Max.
7.7
Unit
ns
Propagation Delay
Bus to Bus
Output Enable Time,
G
,
DIR to Bus
(3)
Output Disable Time,
G
,
DIR to Bus
(3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
Hold Time HIGH or LOW
Bus to Clock
Clock Pulse Width,
HIGH or LOW
2.0
14.0
2.0
15.0
2.0
9.8
2.0
10.5
ns
2.0
9.0
2.0
11.0
2.0
6.3
2.0
7.7
ns
2.0
9.0
2.0
10.0
2.0
6.3
2.0
7.0
ns
2.0
11.0
2.0
12.0
2.0
7.7
2.0
8.4
ns
4.0
—
4.5
—
2.0
—
2.0
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
ns
t
W
6.0
—
6.0
—
5.0
—
5.0
—
ns
646/648/652CT
2646/2652CT
Com'l.
646/652DT
Mil.
Com'l.
Mil.
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
Parameter
Condition
(1)
C
L
= 50pF
R
L
= 500
Min.(2)
1.5
Max.
5.4
Min.(2)
1.5
Max.
6.0
Min.(2)
1.5
Max.
4.4
Min.(2)
—
Max.
—
Unit
ns
Propagation Delay
Bus to Bus
Output Enable Time,
G
,
DIR to Bus
(3)
Output Disable Time,
G
,
DIR to Bus
(3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
Hold Time HIGH or LOW
Bus to Clock
Clock Pulse Width,
HIGH or LOW
(4)
1.5
7.8
1.5
8.9
1.5
5.0
—
—
ns
1.5
6.3
1.5
7.7
1.5
4.3
—
—
ns
1.5
5.7
1.5
6.3
1.5
4.4
—
—
ns
1.5
6.2
1.5
7.0
1.5
5.0
—
—
ns
2.0
—
2.0
—
1.5
—
—
—
ns
t
H
1.5
—
1.5
—
1.0
—
—
—
ns
t
W
5.0
—
5.0
—
3.0
—
—
—
ns
相關(guān)PDF資料
PDF描述
IDT74FCT2652ATEB FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE)
IDT74FCT2652ATL FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE)
IDT74FCT2652ATLB Ceramic Chip Capacitors / Standard Z5U; Capacitance [nom]: 0.01uF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-20%; Dielectric: Multilayer Ceramic; Temperature Coefficient: Z5U; Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: Unmarked
IDT74FCT2652ATP FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE)
IDT74FCT2652ATPB FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE)
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