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參數資料
| 型號： | IDT74FCT273TL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET |
| 中文描述： | FCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| 封裝： | LCC-20 |
| 文件頁數： | 2/7頁 |
| 文件大?。?/td> | 109K |
| 代理商： | IDT74FCT273TL |
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
6.10
2
PIN DESCRIPTION
FUNCTION TABLE
(1)
NOTE:
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑
= LOW-to-HIGH Clock Transition
2568 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
Symbol
C
IN
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
Typ.
6
Max. Unit
10
pF
C
OUT
V
OUT
= 0V
8
12
pF
Symbol
V
TERM(2)
Terminal Voltage
with Respect to
GND
V
TERM(3)
Terminal Voltage
with Respect to
GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
Rating
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
–0.5 to
V
CC
+0.5
–0.5 to
V
CC
+0.5
V
0 to +70
–55 to +125
°
C
–55 to +125
–65 to +135
°
C
–55 to +125
–65 to +150
°
C
0.5
0.5
W
I
OUT
DC Output
Current
–60 to +120 –60 to +120 mA
2568 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
NOTE:
1. This parameter is measured at characterization but not tested.
2568 lnk 04
Inputs
CP
X
↑
↑
Outputs
O
N
L
Operating Mode
Reset (Clear)
MR
D
N
X
L
Load "1"
Load "0"
H
H
h
I
H
L
2568 tbl 01
Pin Names
D
N
MR
Description
Data Inputs
Master Reset (Active LOW)
CP
O
N
Clock Pulse Input (Active Rising Edge)
Data Outputs
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