參數(shù)資料
型號: IDT74FCT374CTQG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/7頁
文件大?。?/td> 0K
描述: IC FLIP FLOP DTYPE OCTAL 20QSOP
標(biāo)準(zhǔn)包裝: 3,000
系列: 74FCT
功能: 標(biāo)準(zhǔn)
類型: D 型總線
輸出類型: 三態(tài)非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
延遲時(shí)間 - 傳輸: 2ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 15mA,48mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
其它名稱: 74FCT374CTQG8
MILITARYANDINDUSTRIALTEMPERATURERANGES
2
IDT54/74FCT374T/AT/CT
FASTCMOSOCTALDREGISTER(3-STATE)
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–60 to +120
mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
COUT
Output Capacitance
VOUT = 0V
8
12
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
LCC
TOP VIEW
2
3
1
16
15
14
11
19
18
20
17
13
12
5
6
7
4
8
9
10
D1
Q0
D0
VCC
Q1
D3
Q2
D2
Q3
GND
Q7
Q6
D7
D6
Q5
Q4
D5
D4
CP
OE
1
2
3
4
5
7
9
6
8
10
11
12
13
14
15
16
17
18
19
20
Q6
D7
D6
Q5
D5
D
0
Q
0
Q
3
GND
CP
Q
4
D
4
OE
V
CC
Q
7
INDEX
D1
Q1
D3
Q2
D2
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
↑ = LOW-to-HIGH transition
FUNCTION TABLE(1)
Inputs
Outputs
Internal
Function
OE
CP
Dx
Qx
High-Z
H
L
X
Z
N C
HH
X
Z
N C
Load
L
LL
H
Register
L
HH
L
H
LZ
H
HZ
L
Pin Names
Description
Dx
D flip-flop data inputs
C P
Clock Pulse for the register. Enters data on LOW-to-
HIGH transition.
Q x
3-State Outputs (TRUE)
Q x
3-State Outputs (INVERTED)
OE
Active LOW 3-State Output Enable Input
PIN DESCRIPTION
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