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參數(shù)資料
| 型號(hào)： | IDT74FCT3827APYB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 10-BIT BUFFERS |
| 中文描述： | 3.3V的CMOS 10位緩沖器 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 102K |
| 代理商： | IDT74FCT3827APYB |
IDT54/74FCT3827A/B
3.3V CMOS OCTAL BUFFERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
8.15
6
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
3. If V
CC
is below 3V, input voltage swings should be adjusted not to exceed
V
CC
.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
SWITCH
GND
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
ETC.
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
GND
6V
←
Open
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
3092 drw 07
3092 drw 05
3092 drw 04
3092 drw 03
3092 drw 06
Test
Switch
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
6V
GND
Open
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
3092 lnk 08
相關(guān)PDF資料 |
PDF描述 |
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| IDT54FCT3827BDB | 3.3V CMOS 10-BIT BUFFERS |
| IDT74FCT3827BDB | 3.3V CMOS 10-BIT BUFFERS |
| IDT54FCT3827A | 3.3V CMOS 10-BIT BUFFERS |
| IDT54FCT3827AD | 3.3V CMOS 10-BIT BUFFERS |
| IDT54FCT3827ADB | 3.3V CMOS 10-BIT BUFFERS |
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