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參數(shù)資料
| 型號(hào)： | IDT74FCT388915T100J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 145K |
| 代理商： | IDT74FCT388915T100J |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
6
NOTES:
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback
configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,
depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the
Q5
output, thus creating a 180
°
phase shift between the SYNC
input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature
and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V. The Q/
2 output was terminated at the FEEDBACK input with 100
to VCC and 100
to ground. tPD measurements were made with the loop filter connection
shown below:
LF
External Loop
Filter
0.1
μ
F
C1
Analog GND
3052 drw 04
FREQ_SEL
Level
HIGH
Feedback
Output
Q/2
Allowable SYNC Input
Frequency Range (MH
Z
)
10 to (2x _Q f
MAX
Spec)/4
Corresponding 2Q Output
Frequency Range
40 to (2Q f
MAX
Spec)
Phase Relationship
of the Q Outputs
to Rising SYNC Edge
0
°
HIGH
Any Q (Q0-Q4)
20 to (2x_Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
0
°
HIGH
Q5
20 to (2x_Q f
MAX
Spec)/2
40 to (2Q f
MAX
Spec)
180
°
HIGH
2X_Q
40 to (2x_Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
0
°
LOW
Q/2
5 to (2x_Q f
MAX
Spec)/8
20 to (2Q f
MAX
Spec)/2
0
°
LOW
Any Q (Q0-Q4)
10 to (2x_Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
0
°
LOW
Q5
10 to (2x_Q f
MAX
Spec)/4
20 to (2Q f
MAX
Spec)/2
180
°
LOW
2X_Q
20 to (2x_Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
0
°
3052 tbl 09
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T100JB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100L | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100LB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100PY | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T100PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT388915T100PY | 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 28 Pin, Plastic, SSOP |
| IDT74FCT388915T150PY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT388915T70J | 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 28 Pin, Plastic, PLCC |
| IDT74FCT388915T70PY | 制造商:Integrated Device Technology 功能描述:74FCT 70MHz 10 to 70MHz Tray |
| IDT74FCT388915TBJG | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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