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參數(shù)資料
| 型號： | IDT74FCT388915T150JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CAP 1.8UF 250/275VAC ECQ-UL |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | 0.050 INCH PITCH, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 145K |
| 代理商： | IDT74FCT388915T150JB |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
8
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4,
Q5
) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
25 MHz
input
50 MHz signal
25 MHz feedback signal
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
signal
OE/RST
3052 drw 10
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
50 MHz feedback signal
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
50 MHz
input
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
input
OE/RST
3052 drw 11
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Output Feedback
Q/2
Q3
Q2
PLL_EN
Q1
Q0
FQ_SEL
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
Q4
Q5
2Q
FCT388915T
LOW
50 MHz signal
12.5 MHz feedback signal
HIGH
HIGH
HIGH
25 MHz
"Q"
Clock
Outputs
12.5 MHz
input
OE/RST
3052 drw 09
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT388915T150PY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT388915T70J | 制造商:Integrated Device Technology Inc 功能描述:EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER, 28 Pin, Plastic, PLCC |
| IDT74FCT388915T70PY | 制造商:Integrated Device Technology 功能描述:74FCT 70MHz 10 to 70MHz Tray |
| IDT74FCT388915TBJG | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT74FCT388915TBJG8 | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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