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參數(shù)資料
| 型號(hào)： | IDT74FST163861PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | CBT/FST/QS/5C/B SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | IDT74FST163861PA8 |
5
INDUSTRIALTEMPERATURERANGE
IDT74FST163861
20-BIT, TWO PORT BUS SWITCH
D.U.T.
VCC
1 MHz
Signal
Generator
CL =
50pF
VOUT
Switch
Out
Enable/Select
Switch In
(MUX)
(1)
Pulse
Generator
R T
D.U.T.
V CC
VIN
C L
VOUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
(2)
(3)
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Charge Injection
NOTES:
1. Select is used with multiplexers for measuring IQDCII during multiplexer select. During
all other tests Enable is used.
2. Used with multiplexers to measure IQDCII only.
3. Charge Injection =
VOUT CL, with Enable toggling for IQCII or Select toggling for IQDCII.
VOUT is the change in VOUT and is measured with a 10M probe.
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