參數(shù)資料
型號(hào): IDT74LVC16244APVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC BUFF DVR TRI-ST 16BIT 48SSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 74LVC
邏輯類型: 緩沖器/線路驅(qū)動(dòng)器,非反相
元件數(shù): 4
每個(gè)元件的位元數(shù): 4
輸出電流高,低: 24mA,24mA
電源電壓: 2.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 帶卷 (TR)
其它名稱: 74LVC16244APVG8
INDUSTRIALTEMPERATURERANGE
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
1
MARCH 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4726/5
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
3.3V CMOS 16-BIT
BUFFER/DRIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
IDT74LVC16244A
DESCRIPTION:
The LVC16244A 16-bit buffer/driver is built using advanced dual metal
CMOS technology. The LVC16244A is designed specifically to improve
both the performance and density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters. The device can be
used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device
provides true outputs and symmetrical active-low output-enable (
OE)
inputs.
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. This feature allows the use of the device as a translator in a mixed
3.3V/5V supply system.
The LVC16244A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
1
A1
1
A2
1
A3
1
A4
1
Y1
1
OE
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Y2
1
Y3
1
Y4
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A1
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A2
2
A3
2
A4
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Y1
2
OE
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Y2
2
Y3
2
Y4
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A1
3
A2
3
A3
3
A4
3
Y1
3
OE
3
Y2
3
Y3
3
Y4
4
A1
4
A2
4
A3
4
A4
4
Y1
4
OE
4
Y2
4
Y3
4
Y4
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