參數(shù)資料
型號: IDT74LVCH16260A
廠商: Integrated Device Technology, Inc.
英文描述: 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
中文描述: 3.3V的CMOS 12位三端口總線交換與5伏的I / O和總線,日用品
文件頁數(shù): 1/7頁
文件大小: 128K
代理商: IDT74LVCH16260A
1
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
MARCH 1999
1999 Integrated Device Technology, Inc.
DSC-4229/1
c
IDT74LVCH16260A
APPLICATIONS:
5V and 3.3V mxed voltage systems
Data communication and telecommunication systems
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual
metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
EXTENDED COMMERCIAL TEMPERATURE RANGE
FEATURES:
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mmpitch SSOP, 0.50mmpitch TSSOP
and 0.40mmpitch TVSOP packages
Extended commercial range of -40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4μW typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
Drive Features for LVCH16260A:
High Output Drivers: ±24mA
Reduced systemswitching noise
3.3V CMOS 12-BIT
TRI-PORT BUS EXCHANGER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
Functional Block Diagram
LE1B
LEA1B
OE1B
SEL
OEA
A
1:12
LE2B
LEA2B
OE2B
A-1B
LATCH
1B-A
LATCH
A-2B
LATCH
2B-A
LATCH
M
U
X
1
0
12
12
12
12
12
12
12
1B
1:12
2B
1:12
12
12
29
30
2
28
1
27
56
55
bus multiplexer/transceiver for use in high-speed mcroprocessor applica-
tions. This bus exchanger supports memory interleaving with latched out-
puts on the B ports and address multiplexing with latched inputs on the B
ports.
The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the B ports. The
latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (
OE1B
and
OE2B
) allow reading fromone port while writing to the other port.
All pins of the 12-bit Bus Exchanger can be driven fromeither 3.3V or
5V devices. This feature allows the use of the device as a translator in a
mxed 3.3V/5V supply system
The LVCH16260A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16260A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and elimnates the need for pull-up/down resistors.
相關(guān)PDF資料
PDF描述
IDT74LVCH16260APA 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
IDT74LVCH16260APF 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
IDT74LVCH16260APV 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
IDT74LVCH16374APV 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
IDT74LVCH16374APA 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
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參數(shù)描述
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