參數(shù)資料
型號(hào): IDT74LVCH16260APA
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 通用總線(xiàn)功能
英文描述: 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
中文描述: LVC/LCX/Z SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封裝: 0.50 MM PITCH, TSSOP-56
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 128K
代理商: IDT74LVCH16260APA
5
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Test Conditions
(1)
Mn.
Max.
0.2
0.4
0.7
0.4
0.55
Unit
V
Output HIGH Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
V
CC
– 0.2
2
1.7
2.2
2.4
2.2
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
V
OL
Output LOW Voltage
V
V
CC
= 2.7V
V
CC
= 3.0V
LVC Link
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
Unit
pF
pF
Power Dissipation Capacitance per bus exchanger Outputs enabled
Power Dissipation Capacitance per bus exchanger Outputs disabled
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V±0.2V
Mn.
1.5
V
CC
= 3.3V±0.3V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
Parameter
Max.
5.7
Mn.
1.5
Max.
5
Unit
ns
Propagation Delay
A
X
to 1B
X
or Ax to 2B
X
Propagation Delay
1B
X
to A
X
or 2B
X
to A
X
Propagation Delay
LE
X
B to A
X
Propagation Delay
LEA1B to 1B
X
or LEA2B to 2B
X
Propagation Delay
SEL to A
X
Output Enable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
Output Disable Time
OEA
to A
X
,
OE1B
to 1B
X,
or
OE2B
to 2B
X
Set-Up Time, HIGH or LOW Data to Latch
Hold Time, Latch to Data
Pulse Width, Latch HIGH
Output Skew
(2)
1.5
6.1
1.5
5.2
ns
1.5
6.1
1.5
5.2
ns
1.5
6.1
1.5
5
ns
1.5
6.3
1.5
5.2
ns
1.5
6.7
1.5
5.5
ns
1.5
5.9
1.5
5.2
ns
1
1
1
3
500
ns
ns
ns
ps
1.2
3
相關(guān)PDF資料
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IDT74LVCH16260APF 3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
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