參數(shù)資料
型號: IDT74LVCH16374APV
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通用總線功能
英文描述: 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
中文描述: LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
封裝: SSOP-48
文件頁數(shù): 2/6頁
文件大?。?/td> 75K
代理商: IDT74LVCH16374APV
INDUSTRIAL TEMPERATURE RANGE
2
IDT74LVCH16374A
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN CONFIGURATION
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Max
Unit
V
°C
mA
mA
Termnal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
mA
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
X = Dont Care
L = LOW Voltage Level
Z = High-Impedance
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
xDx
xCLK
x
OE
xQx
H
L
X
L
L
L
H
L
Q
(2)
H or L
X
X
H
Z
FUNCTION TABLE
(EACH FLIP-FLOP)
(1)
Pin Names
xDx
xCLK
x
OE
xQx
Description
Data Inputs
(1)
Clock Inputs
Output Enable Inputs (Active LOW)
3-State Outputs
PIN DESCRIPTION
1
Q
2
GND
V
CC
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
48
1
1
Q
1
1
OE
1
Q
4
1
Q
3
1
Q
6
1
Q
5
1
Q
8
1
Q
7
2
Q
1
2
Q
3
2
Q
2
2
Q
4
V
CC
2
Q
5
2
Q
6
GND
2
Q
7
2
Q
8
2
OE
1
D
2
GND
V
CC
GND
GND
1
D
1
1
CLK
1
D
4
1
D
3
1
D
6
1
D
5
1
D
8
1
D
7
2
D
1
2
D
3
2
D
2
2
D
4
V
CC
2
D
5
2
D
6
GND
2
D
7
2
D
8
2
CLK
相關(guān)PDF資料
PDF描述
IDT74LVCH16374APA 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
IDT74LVCH16374APF 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD
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