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參數(shù)資料
| 型號(hào)： | IDT74LVCH16374APVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP 16BIT D 3ST 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 74LVCH |
| 功能： | 標(biāo)準(zhǔn) |
| 類型： | D 型 |
| 輸出類型： | 三態(tài)非反相 |
| 元件數(shù)： | 2 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 頻率 - 時(shí)鐘： | 150MHz |
| 延遲時(shí)間 - 傳輸： | 4.5ns |
| 觸發(fā)器類型： | 正邊沿 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74LVCH16374APVG8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16374A
3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
MARCH 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4643/4
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVCH16374A
DESCRIPTION
The LVCH16374A 16-bit edge-triggered D-type register is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (
OE) and clock (CLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
All pins of the LVCH16374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/5V
supply system.
The LVCH16374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT
EDGE-TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS,
5V TOLERANT I/O AND BUS-HOLD
1
OE
1
CLK
1
D1
1
Q1
TO SEVEN OTHER CHANNELS
2
OE
2
CLK
2
D1
2
Q1
1
48
47
2
24
25
36
13
C1
1
D
1
D
C1
TO SEVEN OTHER CHANNELS
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