10
COMMERCIALTEMPERATURERANGE
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
CL = 30 pF
RL = 1K
Ω
DUT
Out
RL = 100
Ω
CLK Inputs
TL = 50
Ω
TL = 350ps, 50
Ω
Test Point
VDD
0V
VDD/2
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
tACT
10%
90%
CLK
VICR
VID
tPLH
tPHL
Output
VOH
VOL
VICR
VTT
VOH
VOL
VIH
VIL
tRPHL
VDD/2
VTT
LVCMOS
RESET
Input
Output
VICR
VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR
VID
tSU
tH
CLK
VDD
RL = 1K
Ω
Test Point
CLK
TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V ± 0.1V)
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA
3. All input pulses are supplied by generators having the following characteristics: PRR
≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times