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參數(shù)資料
| 型號： | IDT74SSTU32864DBFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER 1:1/1:2 96-LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標準包裝： | 270 |
| 邏輯類型： | 1:2 可配置寄存緩沖器 |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 位數(shù)： | 25，14 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 96-LFBGA |
| 供應商設備封裝： | 96-CABGA（13.5x5.5） |
| 包裝： | 托盤 |
| 其它名稱： | 74SSTU32864DBFG |
7
COMMERCIALTEMPERATURERANGE
IDT74SSTU32864/A/C/D/G
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
TERMINAL FUNCTIONS (ALL PINS)
Terminal
Electrical
Name
Characteristics
Description
GND
GroundInput
Ground
VDD
1.8Vnominal
Power Supply Voltage
VREF
0.9Vnominal
InputReferenceVoltage
ZOH(1)
LVCMOS
OutputSlewRateControl
ZOL(1)
LVCMOS
OutputSlewRateControl
CLK
DifferentialInput
Positive Master Clock Input
CLK
DifferentialInput
Negative Master Clock Input
C x
LVCMOS Input
ConfigurationControlInputs
RESET
LVCMOS Input
AsynchronousResetInput. Resetsregistersanddisables VREFdataandclockdifferential-inputreceivers.
CSR, DCS
SSTL_18Input
Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.
Dx
SSTL_18Input
Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
DODT
SSTL_18Input
The outputs of this register bit will not be suspended by the DCS and CSR controls
DCKE
SSTL_18Input
The outputs of this register bit will not be suspended by the DCS and CSR controls
Q x
1.8V CMOS
Data Outputs that are suspended by the DCS and CSR controls
QCSx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
QODTx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
QCKEx
1.8V CMOS
Data Output that will not be suspended by the DCS and CSR controls
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Description
Max.
Unit
VDD
SupplyVoltageRange
–0.5 to 2.5
V
VI(2,3)
InputVoltageRange
–0.5 to 2.5
V
VO(2,3)
OutputVoltageRange
–0.5 to VDD +0.5
V
IIK
InputClampCurrent
VI < 0
±50
mA
VI > VDD
IOK
OutputClampCurrent VO < 0
±50
mA
VO > VDD
IO
ContinuousOutputCurrent,
±50
mA
VO = 0 to VDD
VDD
ContinuousCurrentthrougheach
±100
mA
VDD or GND
TSTG
StorageTemperatureRange
–65to+150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. This value is limited to 2.5V maximum.
NOTE:
1. The signals will be left unconnected for the SSTU32864/A/C/D.
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