參數(shù)資料
型號(hào)： IDT79RC32H434-400BCG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 23/53頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT CORE 400MHZ 256-BGA
標(biāo)準(zhǔn)包裝： 90
系列： Interprise™
處理器類(lèi)型： MIPS32 32-位
速度： 400MHz
電壓： 1.2V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-CABGA（17x17）
包裝： 托盤(pán)
其它名稱(chēng)： 79RC32H434-400BCG
3 of 53
January 19, 2006
IDT RC32434
DMA Controller
The DMA controller consists of 6 independent DMA channels, all of
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, making it appropriate for communications
and graphics systems.
U
UART Interface
ART Interface
The RC32434 contains a serial channel (UART) that is compatible
with the industry standard 16550 UART.
IIII2222C Interface
C Interface
The standard I2C interface allows the RC32434 to connect to a
number of standard external peripherals for a more complete system
solution. The RC32434 supports both master and slave operations.
General Purpose I/O Controller
The RC32434 has 14 general purpose input/output pins. Each pin
may be used as an active high or active low level interrupt or non-
maskable interrupt input, and each signal may be used as a bit input or
output port.
System Integrity Functions
The RC32434 contains a programmable watchdog timer that gener-
ates a non-maskable interrupt (NMI) when the counter expires and also
contains an address space monitor that reports errors in response to
accesses to undecoded address regions.
T
TT
Thermal Considerations
hermal Considerations
The RC32434 is guaranteed in an ambient temperature range of 0
°
to +70
° C for commercial temperature devices and - 40° to +85° for
industrial temperature devices.
Revision Histor
Revision Historyyyy
November 3, 2003: Initial publication. Preliminary Information.
December 15, 2003: Final version. In Table 7, changed maximum
value for Tskew in 266MHz category and changed values for Tdo in all
speed grades for signals DDRADDR, etc. In Table 8, changed minimum
values in all speed grades for all Tdo signals and for Tsu and Tzd in
MDATA[7:0]. In Table 16, added reference to Power Considerations
document. In Table 17, added 2 rows under PCI and Notes 1 and 2.
January 5, 2004: In Table 19, Pin F6 was changed from Vcc I/O to
Vss. In Table 23, pin F6 was deleted from the Vcc I/O row and added to
the Vss row.
January 27, 2004: In Table 3, revised description for MADDR[3:0]
and changed 4096 cycles to 4000 for MADDR[7]. (Note: MADDR was
incorrectly labeled as MDATA in previous data sheet.)
March 29, 2004: Added Standby mode to Table 16, Power
Consumption.
April 19, 2004: Added the I2C feature. In Table 20, pin L1 becomes
SDA and pin L2 becomes SCL.
May 25, 2004: In Table 9, signals MIIRXCLK and MIITXCLK, the Min
and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
December 8, 2005: In Table 18, corrected error for Capacitance Max
value from 8.0 to 10.5.
January 19, 2006: Removed all references to NVRAM.
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