參數資料
型號： IDT79RC32H435-400BCG
廠商： IDT, Integrated Device Technology Inc
文件頁數： 45/53頁
文件大?。?/td> 0K
描述： IC MPU 32BIT CORE 400MHZ 256-BGA
標準包裝： 90
系列： Interprise™
處理器類型： MIPS32 32-位
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應商設備封裝： 256-CABGA（17x17）
包裝： 托盤
其它名稱： 79RC32H435-400BCG
5 of 53
January 19, 2006
IDT 79RC32435
DDRCKP
O
DDR Positive DDR clock. This signal is the positive clock of the differential
DDR clock pair.
DDRCSN
O
DDR Chip Selects. This active low signal is used to select DDR device(s) on
the DDR bus.
DDRDATA[15:0]
I/O
DDR Data Bus. 16-bit DDR data bus is used to transfer data between the
RC32435 and the DDR devices. Data is transferred on both edges of the clock.
DDRDM[1:0]
O
DDR Data Write Enables. Byte data write enables are used to enable specific
byte lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDRDQS[1:0]
I/O
DDR Data Strobes. DDR byte data strobes are used to clock data between
DDR devices and the RC32435. These strobes are inputs during DDR reads
and outputs during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0]
DDRDQS[1] corresponds to DDRDATA[15:8]
DDRRASN
O
DDR Row Address Strobe. The DDR row address strobe is asserted during
DDR transactions.
DDRVREF
I
DDR Voltage Reference. SSTL_2 DDR voltage reference is generated by an
external source.
DDRWEN
O
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
PCI Bus
PCIAD[31:0]
I/O
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCICBEN[3:0]
I/O
PCI Multiplexed Command/Byte Enable Bus. PCI commands are driven by
the bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCICLK
I
PCI Clock. Clock used for all PCI bus transactions.
PCIDEVSELN
I/O
PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCIFRAMEN
I/O
PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCIGNTN[3:0]
I/O
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32435
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32435 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32435 that access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
PCIIRDYN
I/O
PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
Signal
Type
Name/Description
Table 1 Pin Description (Part 2 of 6)
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