參數(shù)資料
型號: IDT79RV4650180MS
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 180 MHz, RISC PROCESSOR, PQFP208
封裝: MQUAD-208
文件頁數(shù): 1/24頁
文件大?。?/td> 1222K
代理商: IDT79RV4650180MS
1998 Integrated Device Technology, Inc.
x High-performance embedded 64-bit microprocessor
-
64-bit integer operations
-
64-bit registers
-
100MHz, 133MHz, 150 MHz, 180MHz, and 200MHz
operation frequencies
x High-performance DSP capability
-
100 Million Integer Multiply-Accumulate Operations/sec
@ 200 MHz
-
67 MFlops floating point operations @200MHz
x High-performance microprocessor
-
100 M Mul-Add/second at 200MHz
-
67 MFLOP/s at 200MHz
-
>500,000 dhrystone (2.1)/sec capability at 200MHz
(265 dhrystone MIPS)
x High level of integration
-
64-bit, 200 MHz integer CPU
-
67MFlops single-precision floating-point unit
-
8KB instruction cache; 8KB data cache
-
Integer multiply unit with 100M Mul-Add/sec
x Low-power operation
-
Active power management powers-down inactive units
-
Standby mode
x Upwardly software compatible with IDT RISController
Family
x Large, efficient on-chip caches
-
Separate 8kB Instruction and 8kB Data caches
-
Over 2400MB/sec bandwidth from internal caches
-
2-set associative
-
Write-back and write-through support
-
Cache locking to facilitate deterministic response
x Bus compatible with RC4000 family
-
System interface provides bandwidth up to 800 MB/S
-
Direct interface to 32-bit wide or 64-bit wide systems
-
Synchronized to external reference clock for multi-master
operation
x Improved real-time support
-
Fast interrupt decode
-
Optional cache locking
August 1998
DSC3149/2
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
200 MIPS 64-bit ORION CPU
64-bit register file
64-bit adder
Store Aligner
Logic Unit
Load aligner
High-Performance
Integer Multiply
P
ipe
li
n
e
C
ont
ro
l
FP register file
FP Add/Sub/Cvt/
Pack/Unpack
FP Multiply
P
ipe
li
n
e
C
o
ntr
o
l
67MFLOPS Single-Precision FPA
Div/Sqrt
32-/64-bit
Synchronized
System Interface
Address Translation/
Cache Attribute Control
Exception Management
Functions
System Control Coprocessor
Data Cache
Instruction Bus
Control Bus
Data Bus
Set A
(Lockable)
Set B
Instruction Cache
Set B
Instruction Cache
Set A
(Lockable)