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參數(shù)資料
| 型號(hào)： | IDT79RV4700-150MS |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 150 MHz, RISC PROCESSOR, PQFP208 |
| 封裝： | MQUAD-208 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 437K |
| 代理商： | IDT79RV4700-150MS |
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
15
AC ELECTRICAL CHARACTERISTICS—R4700
(VCC=5.0V ± 5%; TCASE = 0°C to +85°C)
Clock Parameters—R4700
NOTES TO AC/DC ELECTRICAL CHARACTERISTIC TABLES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.
3. When VIN < 0V or VIN > VCC
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
5. Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
6. Timings are measured from 1.5V of the clock to 1.5V of the signal.
7. Capacitive load for all output timings is 50pF.
8. Guaranteed by design.
9. Typical integer instruction mix and cache miss rates.
10. Operation of the RV4700 is only guaranteed with the Phase Lock Loop enabled.
11. Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
12. Guaranteed by Design.
13. Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
14. Timings are measured from 1.5V of the clock to 1.5V of the signal.
15. Capacitive load for all output timings is 50pF.
16. Typical integer instruction mix and cache miss rates.
17. The maximum bus frequency (Tclock) is 83 MHz.
Parameter
Symbol
Test
Conditions
R4700
80MHz
R4700
100MHz
R4700
133MHz
Units
Min
Max
Min
Max
Min
Max
MasterClock HIGH
tMCHIGH
Transition
≤ t
MCRise
4—
4
—
3
—
ns
MasterClock LOW
tMCLOW
Transition
≤ t
MCFall
4—
4
—
3
—
ns
MasterClock Frequency(5)
—
25
40
25
50
25
67
MHz
MasterClock Period
tMCP
—
2540
2040
15
40
ns
Clock Jitter for Master-
Clock
tJitterIn
(8)
——
±250
—
±250
—
±250
ps
Clock Jitter for
MasterOut, SyncOut,
TClock, RClock
tJitterOut
(8)
——
±500
—
±500
—
±500
ps
MasterClock Rise Time
tMCRise
(8)
——
5.5
—
5
—
4
ns
MasterClock Fall Time
tMCFall
(8)
——
5.5
—
5
—
4
ns
ModeClock Period
tModeCKP
(8)
—
256*tMCP
—
256*tMCP
—
256*tMCP
ns
JTAG Clock Period
tJTAGCKP
(8)
——
4*t MCP
—4*t MCP
ns
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